LSI 53C875A - Manual (Page 19)

LSI53C875A Benefits Summary 1-5
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Ease of Use
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Flexibility
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Reliability
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Testability
1.4.1 SCSI Performance
To improve SCSI performance, the LSI53C875A:
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Has integrated SE transceivers.
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Bursts up to 512 bytes across the PCI bus through its 944 byte FIFO.
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Performs wide, Ultra SCSI synchronous transfers as fast as
40 Mbytes/s.
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Can handle phase mismatches in SCRIPTS without interrupting the
system processor, eliminating the need for CPU intervention during
an I/O disconnect/reselect sequence.
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Achieve Ultra SCSI transfer rates with an input frequency of 20 MHz
with the on-chip SCSI clock quadrupler.
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Includes 4 Kbytes internal RAM for SCRIPTS instruction storage.
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Has 31 levels of SCSI synchronous offset.
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Supports variable block size and scatter/gather data transfers.
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Performs sustained memory-to-memory DMA transfers to
approximately 100 Mbytes/s.
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Minimizes SCSI I/O start latency.
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Performs complex bus sequences without interrupts, including
restoring data pointers.
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Reduces ISR overhead through a unique interrupt status reporting
method.
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Uses Load/Store SCRIPTS instructions which increase performance
of data transfers to and from the chip registers without using PCI
cycles.
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Has SCRIPTS support for 64-bit addressing.
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Supports multithreaded I/O algorithms in SCSI SCRIPTS with fast
I/O context switching.