LSI 53C875A User Manual
Page 61
SCSI Functional Description
2-39
conditions caused the DMA-type interrupt, and clears that DMA interrupt
condition. Bit 7 in DSTAT, DFE, is purely a status bit; it will not generate
an interrupt under any circumstances and will not be cleared when read.
DMA interrupts flush neither the DMA nor SCSI FIFOs before generating
the interrupt, so the DFE bit in the
register should
be checked after any DMA interrupt.
If the DFE bit is cleared, then the FIFOs must be cleared by setting the
CLF (Clear DMA FIFO) and CSF (Clear SCSI FIFO) bits, or flushed by
setting the FLF (Flush DMA FIFO) bit.
SIEN0 and SIEN1 – The
SCSI Interrupt Enable Zero (SIEN0)
and
registers are the interrupt enable registers
for the SCSI interrupts in
SCSI Interrupt Status Zero (SIST0)
and
.
DIEN – The
register is the interrupt enable
register for DMA interrupts in
.
DCNTL – When bit 1 in the
register is set, the
IRQ/ pin is not asserted when an interrupt condition occurs. The interrupt
is not lost or ignored, but is merely masked at the pin. Clearing this bit
when an interrupt is pending immediately causes the IRQ/ pin to assert.
As with any register other than ISTAT, this register cannot be accessed
except by a SCRIPTS instruction during SCRIPTS execution.
2.2.16.3 Fatal vs. Nonfatal Interrupts
A fatal interrupt, as the name implies, always causes the SCRIPTS to
stop running. All nonfatal interrupts become fatal when they are enabled
by setting the appropriate interrupt enable bit. Interrupt masking is
discussed in
All DMA interrupts (indicated
by the DIP bit in ISTAT and one or more bits in
being set) are fatal.
Some SCSI interrupts (indicated by the SIP bit in the
and one or more bits in
or
SCSI Interrupt Status One (SIST1)
being set) are nonfatal.
When the LSI53C875A is operating in the Initiator mode, only the
Function Complete (CMP), Selected (SEL), Reselected (RSL), General