Back-to-back read, 32-bit address and data – LSI 53C875A User Manual
Page 261
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PCI and External Memory Interface Timing Diagrams
6-23
Table 6.23
Back-to-Back Read, 32-Bit Address and Data
Symbol
Parameter
Min
Max
Unit
t
1
Shared signal input setup time
7
–
ns
t
2
Shared signal input hold time
0
–
ns
t
3
CLK to shared signal output valid
2
11
ns
t
4
Side signal input setup time
10
–
ns
t
5
Side signal input hold time
0
–
ns
t
6
CLK to side signal output valid
2
12
ns
t
9
CLK HIGH to GPIO1_MASTER/ LOW
–
20
ns
t
10
CLK HIGH to GPIO1_MASTER/ HIGH
–
20
ns
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