LSI 53C875A - Manual (Page 181)

SCSI Registers 4-89
QSEL SCLK Quadrupler Select 2
This bit, when set, selects the output of the internal clock
quadrupler for use as the internal SCSI clock. When
cleared, this bit selects the clock presented on SCLK for
use as the internal SCSI clock.
R Reserved [1:0]
Register: 0x4E
SCSI Test Two (STEST2)
Read/Write
SCE SCSI Control Enable 7
Setting this bit allows assertion of all SCSI control and
data lines through the
SCSI Output Control Latch (SOCL)
and SCSI Output Data Latch (SODL) registers regardless
of whether the LSI53C875A is configured as a target or
initiator.
Note: Do not set this bit during normal operation, since it could
cause contention on the SCSI bus. It is included for
diagnostic purposes only.
ROF Reset SCSI Offset 6
Setting this bit clears any outstanding synchronous
SREQ/SACK offset. Set this bit if a SCSI gross error
condition occurs and to clear the offset when a
synchronous transfer does not complete successfully.
The bit automatically clears itself after resetting the
synchronous offset.
R Reserved 5
This bit must be cleared.
SLB SCSI Loopback Mode 4
Setting this bit allows the LSI53C875A to perform SCSI
loopback diagnostics. That is, it enables the SCSI core to
simultaneously perform as both the initiator and the
target.
7 6 5 4 3 2 1 0
SCE ROF R SLB SZM AWS EXT LOW
0 0 0 0 0 0 0 0