LSI 53C875A User Manual
Page 52
2-30
Functional Description
bits of the DBC register from the 10-bit value of the DMA FIFO
Byte Offset Counter, which consists of bits [1:0] in the CTEST5
register and bits [7:0] of the DMA FIFO register. AND the result
with 0x3FF for a byte count between zero and 944.
Step 2.
Read bit 5 in the
and
registers to determine if any bytes are left in the
register. If bit 5 is set in the
SSTAT0 or SSTAT2 register, then the least significant byte or
the most significant byte in the SODL register is full,
respectively. Checking this bit also reveals bytes left in the
SODL register from a Chained Move operation with an odd byte
count.
Synchronous SCSI Send –
Step 1.
If the DMA FIFO size is set to 112 bytes (bit 5 of the
register cleared), look at the DFIFO and DBC
registers and calculate if there are bytes left in the DMA FIFO.
To make this calculation, subtract the seven least significant bits
of the
register from the 7-bit value of
the
register. AND the result with 0x7F for
a byte count between zero and 112.
If the DMA FIFO size is set to 944 bytes (bit 5 of the CTEST5
register is set), subtract the 10 least significant bits of the DBC
register from the 10-bit value of the DMA FIFO Byte Offset
Counter, which consists of bits [1:0] in the CTEST5 register and
bits [7:0] of the DMA FIFO register. AND the result with 0x3FF
for a byte count between zero and 944.
Step 2.
Read bit 5 in the
and
registers to determine if any bytes are left in the
register. If bit 5 is set in the
SSTAT0 or SSTAT2 register, then the least significant byte or
the most significant byte in the SODL register is full,
respectively. Checking this bit also reveals bytes left in the
SODL register from a Chained Move operation with an odd byte
count.
Step 3.
Read bit 6 in the
and
registers to determine if any bytes are left in the
SODR register (a hidden buffer register which is not
accessible). If bit 6 is set in the SSTAT0 or SSTAT2 register,