LSI 53C875A User Manual
Page 63
SCSI Functional Description
2-41
Interrupts can be disabled by setting SYNC_IRQD bit 0 in the
register. If an interrupt is already asserted and
SYNC_IRQD is then set, the interrupt will remain asserted until serviced.
At this point, the IRQ/ pin is blocked for future interrupts until this bit is
cleared. When the LSI53C875A is initialized, enable all fatal interrupts if
you are using hardware interrupts. If a fatal interrupt is disabled and that
interrupt condition occurs, the SCRIPTS halt and the system never
knows it unless it times out and checks the ISTAT register after a certain
period of inactivity.
If you are polling the ISTAT instead of using hardware interrupts, then
masking a fatal interrupt makes no difference since the SIP and DIP bits
in the
Interrupt Status Zero (ISTAT0)
inform the system of interrupts, not
the IRQ/ pin.
Masking an interrupt after IRQ/ is asserted does not cause deassertion
of IRQ/.
2.2.16.5 Stacked Interrupts
The LSI53C875A will stack interrupts if they occur one after the other. If
the SIP or DIP bits in the ISTAT register are set (first level), then there is
already at least one pending interrupt, and any future interrupts are
stacked in extra registers behind the
SCSI Interrupt Status Zero (SIST0)
,
SCSI Interrupt Status One (SIST1)
, and
registers
(second level). When two interrupts have occurred and the two levels of
the stack are full, any further interrupts set additional bits in the extra
registers behind
SCSI Interrupt Status Zero (SIST0)
,
, and
. When the first level of
interrupts are cleared, all the interrupts that came in afterward move into
SIST0, SIST1, and DSTAT. After the first interrupt is cleared by reading
the appropriate register, the IRQ/ pin is deasserted for a minimum of
three CLKs; the stacked interrupts move into SIST0, SIST1, or DSTAT;
and the IRQ/ pin is asserted once again.
Since a masked nonfatal interrupt does not set the SIP or DIP bits,
interrupt stacking does not occur. A masked, nonfatal interrupt still posts
the interrupt in SIST0, but does not assert the IRQ/ pin. Since no
interrupt is generated, future interrupts move into
or
SCSI Interrupt Status One (SIST1)
instead of being
stacked behind another interrupt. When another condition occurs that