LSI 53C875A - Manual (Page 98)

4-6 Registers
These bits are read only and should indicate the slowest
time that a device asserts DEVSEL/ for any bus
command except Configuration Read and Configuration
Write. The LSI53C875A supports a value of 0b01.
DPR Data Parity Error Reported 8
This bit is set when all of the following conditions are met:
•
The bus agent asserted PERR/ itself or observed
PERR/ asserted.
•
The agent setting this bit acted as the bus master for
the operation in which the error occurred.
•
The Parity Error Response bit in the Command
register is set.
R Reserved [7:5]
NC New Capabilities 4
This bit is set to indicate a list of extended capabilities
such as PCI Power Management. This bit is read only.
R Reserved [3:0]
Register: 0x08
Revision ID (Rev ID)
Read Only
RID Revision ID [7:0]
This register contains the current revision level of the
device.
7 0
RID
x x x x x x x x