4 phase mismatch jump registers, Phase mismatch jump registers, Section 4.4 “phase mismatch jump registers – LSI 53C875A User Manual
Page 195: Next address 64 (dnad64), Registers: 0xb4–0xb7, Registers: 0xb8–0xbb, Registers: 0xbc–0xbf
Phase Mismatch Jump Registers
4-103
Registers: 0xB4–0xB7
Dynamic Block Move Selector (DBMS)
Read/Write
DBMS
Dynamic Block Move Selector
[31:0]
Supplies the upper Dword of a 64-bit address during
block move operations, reads or writes. This register is
used only during 64-bit direct BMOV instructions and will
be reloaded with the upper 32-bit data address upon
execution of a 64-bit direct BMOVs.
Registers: 0xB8–0xBB
DMA Next Address 64 (DNAD64)
Read/Write
DNAD64
DMA Next Address 64
[31:0]
This register holds the current selector being used in a
given host transaction. The appropriate selector is copied
to this register prior to beginning a host transaction.
Registers: 0xBC–0xBF
Reserved
4.4 Phase Mismatch Jump Registers
Eight 32-bit registers contain the byte count and addressing information
required to update the direct, indirect, or table indirect BMOV instructions
with new byte counts and addresses. The eight register descriptions
follow.
All registers can be read/written using the Load and Store SCRIPTS
instructions, Memory-to-Memory Moves, read/write SCRIPTS
instructions, or the CPU with SCRIPTS not running.
31
0
DBMS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
31
0
DNAD64
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0