LSI 53C875A - Manual (Page 271)

PCI and External Memory Interface Timing Diagrams 6-33
Table 6.28 Burst Write, 64-Bit Address and 32-Bit Data
Symbol Parameter Min Max Unit
t
1
Shared signal input setup time 7 – ns
t
2
Shared signal input hold time 0 – ns
t
3
CLK to shared signal output valid 2 11 ns
t
10
CLK HIGH to GPIO1_MASTER/ HIGH – 20 ns