Intel ARCHITECTURE IA-32 - Manual (Page 116)

IA-32 Intel® Architecture Optimization
2-44
Capacity Limits in Set-Associative Caches
Capacity limits may occur if the number of outstanding memory
references that are mapped to the same set in each way of a given cache
exceeded the number of ways of that cache. The conditions that apply to
the first-level data cache and second level cache are listed below:
• L1 Set Conflicts–multiple references map to the same first-level
cache set. The conflicting condition is a stride determined by the
size of the cache in bytes, divided by the number ways. These
competing memory reference can cause excessive cache misses only
if the number of outstanding memory references exceeds the
number of ways in the working set. On Pentium 4 and Intel Xeon
processors with CPUID signature of family encoding 15, model
encoding of 0, 1 or 2, there will be an excess of first-level cache
misses for more than 4 simultaneous, competing memory references
to addresses with 2KB modulus. On Pentium 4 and Intel Xeon
processors with CPUID signature of family encoding 15, model
encoding 3, excessive first-level cache misses occur when more
than 8 simultaneous, competing references to addresses that are
apart by 2KB modulus. On Pentium M processors, a similar
condition applies to more than 8 simultaneous references to
addresses that are apart by 4KB modulus.
• L2 Set Conflicts – multiple references map to the same second-level
cache set. The conflicting condition is also determined by the size of
the cache/the number of ways. On Pentium 4 and Intel Xeon
processors, excessive second-level cache miss occurs when more
than 8 simultaneous competing references. The stride that can cause
capacity issues are 32KB, 64KB, or 128 KB, depending of the size
of the second level cache. On Pentium M processors, the stride size
that can cause capacity issues are 128 KB or 256 KB, depending of
the size of the second level cache.