Intel ARCHITECTURE IA-32 - Manual (Page 488)

IA-32 Intel® Architecture Optimization
B-34
All WC from the
Processor The number of Write
Combining memory
transactions on the
bus that originated
from this processor.
Beware of granularity
issues with this
event. Also Beware
of different recipes in
mask bits for
Pentium 4 and Intel
Xeon processors
between CPUID
model field value of 2
and model value less
than 2. IOQ_allocation 1a. ReqA0 ,
MEM_WC , OWN
(CPUID model <
2);
1a.
ReqA0 ,ALL_READ,
ALL_WRITE,
MEM_WC , OWN
(CPUID model >=
2)
2. Enable edge
filtering
6 in
the CCCR.
All UC from the
Processor The number of UC
(Uncacheable)
memory transactions
on the bus that
originated from this
processor. User
Note: Beware of
granularity issues.
e.g. a store of
dqword to UC
memory requires two
entries in IOQ
allocation. Also
Beware of different
recipes in mask bits
for Pentium 4 and
Intel Xeon
processors between
CPUID model field
value of 2 and model
value less than 2. IOQ_allocation 1a. ReqA0 ,
MEM_UC , OWN
(CPUID model <
2);
1a.
ReqA0 ,ALL_READ,
ALL_WRITE,
MEM_UC , OWN
(CPUID model >=
2)
2. Enable edge
filtering
6 in
the CCCR.
continued
Table B-1 Pentium 4 Processor Performance Metrics (continued)
Metric Description
Event Name or Metric
Expression Event Mask Value
Required