Intel ARCHITECTURE IA-32 - Manual (Page 47)

IA-32 Intel® Architecture Processor Family Overview
1-19
Caches
The Intel NetBurst microarchitecture supports up to three levels of
on-chip cache. At least two levels of on-chip cache are implemented in
processors based on the Intel NetBurst microarchitecture. The Intel
Xeon processor MP and selected Pentium and Intel Xeon processors
may also contain a third-level cache.
The first level cache (nearest to the execution core) contains separate
caches for instructions and data. These include the first-level data cache
and the trace cache (an advanced first-level instruction cache). All other
caches are shared between instructions and data.
Figure 1-4 Execution Units and Ports in the Out-Of-Order Core
OM15151
ALU 0
Double
Speed
Port 0
ADD/SUB
Logic
Store Data
Branches
FP Move
FP Store Data
FXCH
ALU 1
Double
Speed
ADD/SUB Shift/Rotate
FP
Execute
FP_ADD
FP_MUL
FP_DIV
FP_MISC
MMX_SHFT
MMX_ALU
MMX_MISC
Port 1
M em ory
Store
M em ory
Load
All Loads
Prefetch
Port 2 Port 3
Store
Address
FP
M ove
Integer
Operation
Norm al
Speed
Note:
FP_ADD refers to x87 FP, and SIMD FP add and subtract operations
FP_MUL refers to x87 FP, and SIMD FP m ultiply operations
FP_D IV refers to x87 FP, and SIMD FP divide and square root operations
MMX_ALU refers to SIMD integer arithm etic and logic operations
MMX_SHFT handles Shift, Rotate, Shuffle, Pack and U npack operations
MMX_MISC handles SIMD reciprocal and som e integer operations