Intel ARCHITECTURE IA-32 - Manual (Page 64)

IA-32 Intel® Architecture Optimization
1-36
Processor Resources and Hyper-Threading Technology
The majority of microarchitecture resources in a physical processor are
shared between the logical processors. Only a few small data structures
were replicated for each logical processor. This section describes how
resources are shared, partitioned or replicated.
Replicated Resources
The architectural state is replicated for each logical processor. The
architecture state consists of registers that are used by the operating
system and application code to control program behavior and store data
for computations. This state includes the eight general-purpose
registers, the control registers, machine state registers, debug registers,
and others. There are a few exceptions, most notably the memory type
range registers (MTRRs) and the performance monitoring resources.
For a complete list of the architecture state and exceptions, see the IA-32
Intel® Architecture Software Developer’s Manual, Volumes 3A & 3B.
Other resources such as instruction pointers and register renaming tables
were replicated to simultaneously track execution and state changes of
the two logical processors. The return stack predictor is replicated to
improve branch prediction of return instructions.
In addition, a few buffers (for example, the 2-entry instruction
streaming buffers) were replicated to reduce complexity.
Partitioned Resources
Several buffers are shared by limiting the use of each logical processor
to half the entries. These are referred to as partitioned resources.
Reasons for this partitioning include:
• operational fairness
• permitting the ability to allow operations from one logical processor
to bypass operations of the other logical processor that may have
stalled