Intel ARCHITECTURE IA-32 - Manual (Page 401)

Multi-Core and Hyper-Threading Technology
7
7-55
Example 7-13 Discovering the Affinity Masks for Sibling Logical Processors
Sharing the Same Cache
// Logical processors sharing the same cache can be determined by bucketing
// the logical processors with a mask, the width of the mask is determined
// from the maximum number of logical processors sharing that cache level.
// The algorithm below assumes that all processors have identical cache hierarchy
// and initial APIC ID assignment across the modular
// boundary of the logical processor sharing the target level cache must respect
// bit-field boundary. This is a requirement similar to those applying to
// core boundary and package boundary. The modular boundary of those
// logical processors sharing the target level cache may coincide with core
// boundary or above core boundary.
ThreadAffinityMask = 1;
ProcessorNum = 0;
while (ThreadAffinityMask != 0 && ThreadAffinityMask <=
SystemAffinity) {
// Check to make sure we can utilize this processor first.
if (ThreadAffinityMask & SystemAffinity){
Set thread to run on the processor specified in
ThreadAffinityMask.
Wait if necessary and ensure thread is running on specified
processor.
initialAPIC_ID = GetInitialAPIC_ID();
Extract the Package, Core and SMT ID as explained in
three level extraction algorithm.
Extract the CACHE_ID similar to the PACKAGE_ID extraction algorithm.
// Cache topology may vary for each cache level, one mask for each level.
// The target level is selected by the input value index
CacheIDMask = ((uchar) (0xff <<
FindMaskWidth(MaxLPSharingCache(TargetLevel))); // See Example 7-9.
CACHE_ID = InitialAPIC_ID & CacheIDMask;