Intel ARCHITECTURE IA-32 User Manual
Page 524
IA-32 Intel® Architecture Optimization
C-10
COMISD xmm, xmm
7
6
1
2
2
1
FP_ADD,
FP_MISC
CVTDQ2PD xmm, xmm
8
8
4+1
3
3
4
FP_ADD,
MMX_SHFT
CVTPD2PI mm, xmm
12
11
5
3
3
3
FP_ADD,
MMX_SHFT,
MMX_ALU
CVTPD2DQ xmm, xmm
10
9
5
2
2
3
FP_ADD,
MMX_SHFT
CVTPD2PS
3
xmm, xmm
11
10
2
2
FP_ADD,
MMX_SHFT
CVTPI2PD xmm, mm
12
11
4+1
2
4
4
FP_ADD,
MMX_SHFT,
MMX_ALU
CVTPS2PD
3
xmm, xmm
3
2
2+1
2
3
FP_ADD,
MMX_SHFT,
MMX_ALU
CVTSD2SI r32, xmm
9
8
2
2
FP_ADD,
FP_MISC
CVTSD2SS
3
xmm, xmm
17
16
4
2
4
1
FP_ADD,
MMX_SHFT
CVTSI2SD
3
xmm, r32
16
15
4
2
3
1
FP_ADD,
MMX_SHFT,
MMX_MISC
CVTSS2SD
3
xmm, xmm
9
8
2
2
2
2
CVTTPD2PI mm, xmm
12
11
5
3
3
3
FP_ADD,
MMX_SHFT,
MMX_ALU
CVTTPD2DQ xmm, xmm
10
9
2
2
FP_ADD,
MMX_SHFT
CVTTSD2SI r32, xmm
8
8
2
2
FP_ADD,
FP_MISC
continued
Table C-3
Streaming SIMD Extension 2 Double-precision Floating-point
Instructions (continued)
Instruction
Latency
1
Throughput
Execution
Unit
2