Intel ARCHITECTURE IA-32 - Manual (Page 508)

IA-32 Intel® Architecture Optimization
B-54
Bus Metrics Bus Accesses from the Processor 1
Non-prefetch Bus Accesses from the Processor 1
Reads from the Processor 1
Writes from the Processor 1
Reads Non-prefetch from the Processor 1
All WC from the Processor 1
All UC from the Processor 1
Bus Accesses from All Agents 1
Bus Accesses Underway from the processor 1
Bus Reads Underway from the processor 1
Non-prefetch Reads Underway from the processor 1
All UC Underway from the processor 1
All WC Underway from the processor 1
Bus Writes Underway from the processor 1
Bus Accesses Underway from All Agents 1
Write WC Full (BSQ) 1
Write WC Partial (BSQ) 1
Writes WB Full (BSQ) 1
Reads Non-prefetch Full (BSQ) 1
Reads Invalidate Full- RFO (BSQ) 1
UC Reads Chunk (BSQ) 1
UC Reads Chunk Split (BSQ) 1
UC Write Partial (BSQ) 1
IO Reads Chunk (BSQ) 1
IO Writes Chunk (BSQ) 1
WB Writes Full Underway (BSQ) 1
UC Reads Chunk Underway (BSQ) 1
Write WC Partial Underway(BSQ) 1
continued
Table B-6 Metrics That Support Qualification by Logical Processor and
Parallel Counting (continued)