Intel ARCHITECTURE IA-32 - Manual (Page 70)

IA-32 Intel® Architecture Optimization
1-42
Microarchitecture Pipeline and Multi-Core Processors
In general, each core in a multi-core processor resembles a single-core
processor implementation of the underlying microarchitecture. The
implementation of the cache hierarchy in a dual-core or multi-core
processor may be the same or different from the cache hierarchy
implementation in a single-core processor.
CPUID should be used to determine cache-sharing topology
information in a processor implementation and the underlying
microarchitecture. The former is obtained by querying the deterministic
cache parameter leaf (see Chapter 6, “Optimizing Cache Usage”); the
latter by using the encoded values for extended family, family, extended
model, and model fields. See Table 1-4.
Shared Cache in Intel Core Duo Processors
The Intel Core Duo processor has two symmetric cores that share the
second-level cache and a single bus interface (see Figure 1-7). Two
threads executing on two cores in an Intel Core Duo processor can take
advantage of shared second-level cache, accessing a single-copy of
cached data without generating bus traffic.
Load and Store Operations
When an instruction needs to read data from a memory address, the
processor looks for it in caches and memory. When an instruction writes
data to a memory location (write back) the processor first makes sure
Table 1-4 Family And Model Designations of Microarchitectures
Dual-Core
Processor Micro-
architecture Extended
Family
Family
Extended
Model
Model
Pentium D processor NetBurst 0 15 0 3, 4, 6
Pentium processor
Extreme Edition NetBurst 0 15 0 3, 4, 6
Intel Core Duo
processor Improved
Pentium M 0 6 0 14