Intel ARCHITECTURE IA-32 - Manual (Page 531)

IA-32 Instruction Latency and Throughput
C
C-17
FSCALE 4 60 7
FRNDINT 4 30 11
FXCH 5 0 1 FP_MOVE
FLDZ 6 0
FINCSTP/FDECSTP 6 0
See “Table Footnotes”
Table C-8 IA-32 General Purpose Instructions
Instruction Latency 1 Throughput Execution Unit 2
CPUID 0F3n 0F2n 0x69n 0F3n 0F2n 0x69n 0F2n
ADC/SBB reg, reg 8 8 3 3
ADC/SBB reg, imm 8 6 2 2 ALU
ADD/SUB 1 0.5 0.5 0.5 ALU
AND/OR/XOR 1 0.5 0.5 0.5 ALU
BSF/BSR 16 8 2 4
BSWAP 1 7 0.5 1 ALU
BTC/BTR/BTS 8-9 1
CLI 26
CMP/TEST 1 0.5 0.5 0.5 ALU
DEC/INC 1 1 0.5 0.5 ALU
IMUL r32 10 14 4 1 3 FP_MUL
IMUL imm32 14 4 1 3 FP_MUL
IMUL 15-18 4 5
IDIV 66-80 56-70 30 23
IN/OUT 1 <225 40
continued
Table C-7 IA-32 x87 Floating-point Instructions (continued)
Instruction Latency 1 Throughput
Execution
Unit
2