Intel ARCHITECTURE IA-32 - Manual (Page 480)

IA-32 Intel® Architecture Optimization
B-26
64K Aliasing
Conflicts
1
The number of 64K
aliasing conflicts. A
memory reference
causing 64K aliasing
conflict can be
counted more than
once in this stat. The
performance penalty
resulted from
64K-aliasing conflict
can vary from being
unnoticeable to
considerable. Some
implementations of
the Pentium 4
processor family can
incur significant
penalties for loads
that alias to
preceding stores. Memory_cancel 64K_CONF
Split Load
Replays The number of load
references to data
that spanned two
cache lines. Memory_complete LSC
Split Loads
Retired The number of
retired load
μops that
spanned two cache
lines.
Replay_event ; set the
following replay tag:
Split_load_retired
.
NBOGUS
Split Store
Replays The number of store
references that
spans across cache
line boundary. Memory_complete SSC
Split Stores
Retired The number of
retired store
μops
that spanned two
cache lines.
Replay_event ; set the
following replay tag:
Split_store_retired
.
NBOGUS
continued
Table B-1 Pentium 4 Processor Performance Metrics (continued)
Metric Description
Event Name or Metric
Expression Event Mask Value
Required