Intel ARCHITECTURE IA-32 - Manual (Page 242)

IA-32 Intel® Architecture Optimization
4-22
pxor MM0, MM0
pcmpeq MM1, MM1
psubb MM0, MM1 [psubw MM0, MM1] (psubd MM0, MM1)
; three instructions above generate
; the constant 1 in every
; packed-byte [or packed-word]
; (or packed-dword) field
pcmpeq MM1, MM1
psrlw MM1, 16-n(psrld MM1, 32-n)
; two instructions above generate
; the signed constant 2 n –1 in every
; packed-word (or packed-dword) field
pcmpeq MM1, MM1
psllw MM1, n (pslld MM1, n)
; two instructions above generate
; the signed constant -2n in every
; packed-word (or packed-dword) field
NOTE. Because the SIMD integer instruction sets do
not support shift instructions for bytes, 2 n –1 and -2 n
are relevant only for packed words and packed
doublewords.
Example 4-15 Generating Constants (continued)