Intel ARCHITECTURE IA-32 - Manual (Page 482)

IA-32 Intel® Architecture Optimization
B-28
2nd-Level
Cache Reads
Hit Shared The number of
2nd-level cache read
references (loads
and RFOs) that hit
the cache line in
shared state. Beware
of granularity
differences. BSQ_cache_reference RD_2ndL_HITS
2nd-Level
Cache Reads
Hit Modified The number of
2nd-level cache read
references (loads
and RFOs) that hit
the cache line in
modified state.
Beware of granularity
differences. BSQ_cache_reference RD_2ndL_HITM
2nd-Level
Cache Reads
Hit Exclusive The number of
2nd-level cache read
references (loads
and RFOs) that hit
the cache line in
exclusive state.
Beware of granularity
differences. BSQ_cache_reference RD_2ndL_HITE
3rd-Level
Cache Reads
Hit Shared The number of
3rd-level cache read
references (loads
and RFOs) that hit
the cache line in
shared state. Beware
of granularity
differences. BSQ_cache_reference RD_3rdL_HITS
continued
Table B-1 Pentium 4 Processor Performance Metrics (continued)
Metric Description
Event Name or Metric
Expression Event Mask Value
Required