Intel ARCHITECTURE IA-32 - Manual (Page 485)

Using Performance Monitoring Events
B
B-31
Bus Metrics
Bus Accesses
from the
Processor The number of all
bus transactions that
were allocated in the
IO Queue from this
processor. Beware of
granularity issues
with this event. Also
Beware of different
recipes in mask bits
for Pentium 4 and
Intel Xeon
processors between
CPUID model field
value of 2 and model
value less than 2. IOQ_allocation 1a. ReqA0 ,
ALL_READ ,
ALL_WRITE , OWN,
PREFETCH (CPUID
model < 2);
1b.ReqA0,
ALL_READ
,
ALL_WRITE,
MEM_WB, MEM_WT,
MEM_WP, MEM_WC,
MEM_UC , OWN,
PREFETCH (CPUID
model >= 2).
2. Enable edge
filtering 6 in
the CCCR.
Non-prefetch
Bus Accesses
from the
Processor The number of all
bus transactions that
were allocated in the
IO Queue from this
processor excluding
prefetched sectors.
Beware of granularity
issues with this
event. Also Beware
of different recipes in
mask bits for
Pentium 4 and Intel
Xeon processors
between CPUID
model field value of 2
and model value less
than 2. IOQ_allocation 1a. ReqA0 ,
ALL_READ ,
ALL_WRITE , OWN
(CPUID model <
2);
1b. ReqA0 ,
ALL_READ ,
ALL_WRITE,
MEM_WB, MEM_WT,
MEM_WP, MEM_WC,
MEM_UC , OWN
(CPUID model <
2).
2. Enable edge
filtering 6 in
the CCCR.
continued
Table B-1 Pentium 4 Processor Performance Metrics (continued)
Metric Description
Event Name or Metric
Expression Event Mask Value
Required