Intel ARCHITECTURE IA-32 - Manual (Page 332)

IA-32 Intel® Architecture Optimization
6-42
selected to ensure that the batch stays within the processor caches
through all passes. An intermediate cached buffer is used to pass the
batch of vertices from one stage or pass to the next one.
Single-pass execution can be better suited to applications which limit
the number of features that may be used at a given time. A single-pass
approach can reduce the amount of data copying that can occur with a
multi-pass engine, see Figure 6-8.
Figure 6-8 Single-Pass Vs. Multi-Pass 3D Geometry Engines
Transform
Lighting
Single-Pass
Culling
Lighting
Multi-Pass
Culling
40 vis
40 vis
60 invis
80 vis
80 vis
Vertex
processing
(inner loop)
Outer loop is
processing
strips
Transform
strip list