Intel ARCHITECTURE IA-32 - Manual (Page 21)

xxi
Tables
Table 1-1 Pentium 4 and Intel Xeon Processor Cache Parameters .................. 1-20
Table 1-3 Cache Parameters of Pentium M, Intel
®
Core™ Solo and
Intel
®
Core™ Duo Processors .......................................................... 1-30
Table 1-2 Trigger Threshold and CPUID Signatures for IA-32
Processor Families ............................................................................ 1-30
Table 1-4 Family And Model Designations of Microarchitectures...................... 1-42
Table 1-5 Characteristics of Load and Store Operations
in Intel Core Duo Processors ............................................................ 1-43
Table 2-1 Coding Pitfalls Affecting Performance ................................................. 2-2
Table 2-2 Avoiding Partial Flag Register Stall ................................................... 2-76
Table 2-3 Avoiding Partial Register Stall When Packing Byte Values ............... 2-78
Table 2-4 Avoiding False LCP Delays with 0xF7 Group Instructions ................ 2-81
Table 2-5 Using REP STOSD with Arbitrary Count Size and
4-Byte-Aligned Destination................................................................ 2-85
Table 5-1 SoA Form of Representing Vertices Data ........................................... 5-7
Table 6-1 Software Prefetching Considerations into Strip-mining Code............ 6-39
Table 6-2 Relative Performance of Memory Copy Routines ............................. 6-52
Table 6-3 Deterministic Cache Parameters Leaf............................................... 6-54
Table 7-1 Properties of Synchronization Objects .............................................. 7-21
Table B-1 Pentium 4 Processor Performance Metrics .......................................B-18
Table B-2 Metrics That Utilize Replay Tagging Mechanism...............................B-47
Table B-3 Table 3 Metrics That Utilize the Front-end Tagging Mechanism ........B-48
Table B-4 Metrics That Utilize the Execution Tagging Mechanism ....................B-49
Table B-5 New Metrics for Pentium 4 Processor (Family 15, Model 3)..............B-50
Table B-6 Metrics That Support Qualification by Logical Processor and
Parallel Counting ...............................................................................B-51
Table B-7 Metrics That Are Independent of Logical Processors........................B-55
Table C-1 Streaming SIMD Extension 3 SIMD Floating-point Instructions ......... C-6
Table C-2 Streaming SIMD Extension 2 128-bit Integer Instructions.................. C-7
Table C-3 Streaming SIMD Extension 2 Double-precision Floating-point
Instructions ......................................................................................... C-9
Table C-4 Streaming SIMD Extension Single-precision Floating-point
Instructions ....................................................................................... C-12
Table C-6 MMX Technology 64-bit Instructions ................................................ C-14