Intel ARCHITECTURE IA-32 - Manual (Page 463)

Using Performance Monitoring Events
B
B-9
There is a simplified block diagram below of the sub-systems connected
to the IOQ unit in the front side bus sub-system and the BSQ unit that
interface to the IOQ. A two-way SMP configuration is illustrated.
1st-level cache misses and writebacks (also called core references)
result in references to the 2nd-level cache. The Bus Sequence Queue
(BSQ) holds requests from the processor core or prefetcher that are to be
serviced on the front side bus (FSB), or in the local XAPIC. If a
3rd-level cache is present on-die, the BSQ also holds writeback requests
(dirty, evicted data) from the 2nd-level cache. The FSB's IOQ holds
requests that have gone out onto the front side bus.