Intel ARCHITECTURE IA-32 - Manual (Page 564)

IA-32 Intel® Architecture Optimization
Index-4
L
large load stalls, 2-37
latency, 2-72, 6-5
lea instruction, 2-74
loading and storing to and from the same
DRAM page, 4-39
loop blocking, 3-34
loop unrolling, 2-26
loop unrolling option, A-5, A-6
M
memory bank conflicts, 6-3
memory O=optimization U=using P=prefetch,
6-18
memory operands, 2-71
memory optimization, 4-34
memory optimizations
loading and storing to and from the same
DRAM page, 4-39
partial memory accesses, 4-35
using aligned stores, 4-40
memory performance, 3-27
memory reference instructions, 2-86
memory throughput bound, E-10
micro-op fusion, 1-32
minimizing prefetches number, 6-29
misaligned data access, 3-20
misalignment in the FIR filter, 3-22
mobile computing
ACPI standard, 9-1
active power, 9-1
battery life, 9-1, 9-7
OS APIs, 9-8
C4-state, 9-6
CD/DVD, WLAN, WiFi, 9-10
C-states, 9-1, 9-4
deep sleep transitions, 9-11
deeper sleep, 9-6, 9-14
OS changes processor frequency, 9-2
OS synchronization APIs, 9-9
overview, 9-1
performance options, 9-8
platform optimizations, 9-10
P-states, 9-1
Speedstep technology, 9-12
spin loops, 9-9
static power, 9-1
WM_POWERBROADCAST message,
9-11
moble computing
state transitions, 9-2
move byte mask to integer, 4-16
MOVQ Instruction, 4-39
multi-core features, 1-39
N
new SIMD-integer instructions
extract word, 4-13
insert word, 4-14
move byte mask to integer, 4-16
packed average byte or word), 4-31
packed multiply high unsigned, 4-30
packed shuffle word, 4-18
packed signed integer word maximum, 4-29
packed sum of absolute differences, 4-30
Newton-Raphson iteration, 5-2
non-coherent requests, 6-13
non-interleaved unpack, 4-11
non-temporal stores, 6-43
NOPs, 2-95
To align instructions, 2-95
XCHG EAX,EAX
Special hardware support for, 2-95
numeric exceptions
flush to zero, 5-22