Intel ARCHITECTURE IA-32 - Manual (Page 255)

Optimizing for SIMD Integer Applications
4
4-35
Partial Memory Accesses
Consider a case with large load after a series of small stores to the same
area of memory (beginning at memory address
mem ). The large load will
stall in this case as shown in Example 4-24.
The movq must wait for the stores to write memory before it can access
all the data it requires. This stall can also occur with other data types
(for example, when bytes or words are stored and then words or
doublewords are read from the same area of memory). When you
change the code sequence as shown in Example 4-25, the processor can
access the data without delay.
Example 4-24 A Large Load after a Series of Small Stores (Penalty)
mov mem, eax ; store dword to address “mem"
mov mem + 4, ebx ; store dword to address “mem + 4"
:
:
movq mm0, mem ; load qword at address “mem", stalls
Example 4-25 Accessing Data without Delay
movd mm1, ebx ; build data into a qword first
; before storing it to memory
movd mm2, eax
psllq mm1, 32
por mm1, mm2
movq mem, mm1 ; store SIMD variable to “mem" as
; a qword
:
:
movq mm0, mem ; load qword SIMD “mem", no stall