Intel ARCHITECTURE IA-32 - Manual (Page 254)

IA-32 Intel® Architecture Optimization
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Memory Optimizations
You can improve memory accesses using the following techniques:
• Avoiding partial memory accesses
• Increasing the bandwidth of memory fills and video fills
• Prefetching data with Streaming SIMD Extensions (see Chapter 6,
“Optimizing Cache Usage”).
The MMX registers and XMM registers allow you to move large
quantities of data without stalling the processor. Instead of loading
single array values that are 8, 16, or 32 bits long, consider loading the
values in a single quadword or double quadword, then incrementing the
structure or array pointer accordingly.
Any data that will be manipulated by SIMD integer instructions should
be loaded using either:
• the SIMD integer instruction that loads a 64-bit or 128-bit operand
(for example,
movq MM0, m64 )
• the register-memory form of any SIMD integer instruction that
operates on a quadword or double quadword memory operand (for
example,
pmaddw MM0 , m64 ).
All SIMD data should be stored using the SIMD integer instruction that
stores a 64-bit or 128-bit operand (for example,
movq m64, MM0 )
The goal of these recommendations is twofold. First, the loading and
storing of SIMD data is more efficient using the larger block sizes.
Second, this helps to avoid the mixing of 8-, 16-, or 32-bit load and store
operations with SIMD integer technology load and store operations to
the same SIMD data. This, in turn, prevents situations in which small
loads follow large stores to the same area of memory, or large loads
follow small stores to the same area of memory. The Pentium II,
Pentium III, and Pentium 4 processors stall in these situations; see
Chapter 2, “General Optimization Guidelines” for more details.