Intel ARCHITECTURE IA-32 - Manual (Page 344)

IA-32 Intel® Architecture Optimization
6-54
query each level of the cache hierarchy. Enumeration of each cache
level is by specifying an index value (starting form 0) in the ECX
register. The list of parameters is shown in Table 6-3.
The deterministic cache parameter leaf provides a means to implement
software with a degree of forward compatibility with respect to
enumerating cache parameters.
The deterministic cache parameters can be used in several situations,
including:
• Determine the size of a cache level.
• Adapt cache blocking parameters to different sharing topology of a
cache-level across Hyper-Threading Technology, multicore and
single-core processors.
Table 6-3 Deterministic Cache Parameters Leaf
Bit Location Name Meaning
EAX[4:0] Cache Type 0 = Null - No more caches
1 = Data Cache
2 = Instruction Cache
3 = Unified Cache
4-31 = Reserved
EAX[7:5] Cache Level Starts at 1
EAX[8] Self Initializing cache level 1: does not need SW
initialization
EAX[9] Fully Associative cache 1: Yes
EAX[13:10] Reserved
EAX[25:14] Maximum number of logical processors
sharing this cache Plus 1 encoding
EAX[31:26] Maximum number of cores in a package Plus 1 encoding
EBX[11:0] System Coherency Line Size (L) Plus 1 encoding (Bytes)
EBX[21:12] Physical Line partitions (P) Plus 1 encoding
EBX[31:22] Ways of associativity (W) Plus 1 encoding
ECX[31:0] Number of Sets (S) Plus 1 encoding
EDX Reserved
NOTE: CPUID leaves > 3 < 80000000 are only visible when
IA32_CR_MISC_ENABLES.BOOT_NT4 (bit 22) is clear (Default)