Intel ARCHITECTURE IA-32 - Manual (Page 57)

IA-32 Intel® Architecture Processor Family Overview
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• Micro-ops (µops) fusion. Some of the most frequent pairs of µops
derived from the same instruction can be fused into a single µops.
The following categories of fused µops have been implemented in
the Pentium M processor:
— “Store address” and “store data” micro-ops are fused into a
single “Store” micro-op. This holds for all types of store
operations, including integer, floating-point, MMX technology,
and Streaming SIMD Extensions (SSE and SSE2) operations.
— A load micro-op in most cases can be fused with a successive
execution micro-op.This holds for integer, floating-point and
MMX technology loads and for most kinds of successive
execution operations. Note that SSE Loads can not be fused.
Data Prefetching
The Intel Pentium M processor supports three prefetching mechanisms:
• The first mechanism is a hardware instruction fetcher and is
described in the previous section.
• The second mechanism automatically fetches data into the
second-level cache. The implementation of automatic hardware
prefetching in Pentium M processor family is basically similar to
those described for NetBurst microarchitecture. The trigger
threshold distance for each relevant processor models is shown in
Table 1-2
• The third mechanism is a software mechanism that fetches data into
the caches using the prefetch instructions.