Intel ARCHITECTURE IA-32 - Manual (Page 313)

Optimizing Cache Usage
6
6-23
execution units sit idle and wait until data is returned. On the other hand,
the memory bus sits idle while the execution units are processing
vertices. This scenario severely decreases the advantage of having a
decoupled architecture.
Figure 6-2 Memory Access Latency and Execution Without Prefetch
Figure 6-3 Memory Access Latency and Execution With Prefetch
O M15170
Execution units idle
M em latency
Issue loads
Tim e
Vertex n+1
Execution units idle
Execution
pipeline
M em latency
Issue loads
(vertex data)
Vertex n
Front-Side
Bus
FSB idle
O M15171
Tim e
Vertex n-2
Execution
pipeline
Mem latency for V
n
issue prefetch
for vertex n
Front-Side
Bus
Vertex n-1 Vertex n Vertex n+1
Mem latency for V
n+1
Mem latency for V
n+2
prefetch
V
n+1
prefetch
V
n+2