Intel ARCHITECTURE IA-32 - Manual (Page 369)

Multi-Core and Hyper-Threading Technology
7
7-23
the processor must guarantee no violations of memory order occur. The
necessity of maintaining the order of outstanding memory operations
inevitably costs the processor a severe penalty that impacts all threads.
This penalty occurs on the Pentium M processor, the Intel Core Solo and
Intel Core Duo processors. However, the penalty on these processors is
small compared with penalties suffered on the Pentium 4 and Intel Xeon
processors. There the performance penalty for exiting the loop is about
25 times more severe.
On a processor supporting Hyper-Threading Technology, spin-wait
loops can consume a significant portion of the execution bandwidth of
the processor. One logical processor executing a spin-wait loop can
severely impact the performance of the other logical processor.