Intel ARCHITECTURE IA-32 - Manual (Page 486)

IA-32 Intel® Architecture Optimization
B-32
Prefetch Ratio Fraction of all bus
transactions
(including retires)
that were for HW or
SW prefetching. (Bus Accesses –
Nonprefetch Bus
Accesses)/ (Bus
Accesses)
FSB Data
Ready The number of
front-side bus clocks
that the bus is
transmitting data
driven by this
processor (includes
full reads|writes and
partial reads|writes
and implicit
writebacks). FSB_data_activity 1. DRDY_OWN,
DRDY_DRV
2. Enable edge
filtering
6 in
the CCCR.
Bus Utilization The % of time that
the bus is actually
occupied (FSB Data Ready)
*Bus_ratio*100/
Non-Sleep Clockticks
Reads from the
Processor The number of all
read (includes
RFOs) transactions
on the bus that were
allocated in IO
Queue from this
processor (includes
prefetches). Beware
of granularity issues
with this event. Also
Beware of different
recipes in mask bits
for Pentium 4 and
Intel Xeon
processors between
CPUID model field
value of 2 and model
value less than 2. IOQ_allocation 1a. ReqA0 ,
ALL_READ ,
OWN , PREFETCH
(CPUID model <
2);
1b. ReqA0 ,
ALL_READ,
MEM_WB, MEM_WT,
MEM_WP, MEM_WC,
MEM_UC ,
OWN , PREFETCH
(CPUID model >=
2);
2. Enable edge
filtering
6 in
the CCCR.
continued
Table B-1 Pentium 4 Processor Performance Metrics (continued)
Metric Description
Event Name or Metric
Expression Event Mask Value
Required