Intel ARCHITECTURE IA-32 - Manual (Page 240)

IA-32 Intel® Architecture Optimization
4-20
Unpacking/interleaving 64-bit Data in 128-bit Registers
The punpcklqdq / punpchqdq instructions interleave the low/high-order
64-bits of the source operand and the low/high-order 64-bits of the
destination operand and writes them to the destination register. The
high/low-order 64-bits of the source operands are ignored.
Example 4-13 Swap Using 3 Instructions
/* Goal: Swap the values in word 6 and word 1 */
/* Instruction Result */
| 7| 6| 5| 4| 3| 2| 1| 0|
PSHUFD (3,0,1,2)| 7| 6| 1| 0| 3| 2| 5| 4|
PSHUFHW (3,1,2,0)| 7| 1| 6| 0| 3| 2| 5| 4|
PSHUFD (3,0,1,2)| 7| 1| 5| 4| 3| 2| 6| 0|
Example 4-14 Reverse Using 3 Instructions
/* Goal: Reverse the order of the words */
/* Instruction Result */
| 7| 6| 5| 4| 3| 2| 1| 0|
PSHUFLW (0,1,2,3)| 7| 6| 5| 4| 0| 1| 2| 3|
PSHUFHW (0,1,2,3)| 4| 5| 6| 7| 0| 1| 2| 3|
PSHUFD (1,0,3,2)| 0| 1| 2| 3| 4| 5| 6| 7|