Intel ARCHITECTURE IA-32 - Manual (Page 296)

IA-32 Intel® Architecture Optimization
6-6
Data reference patterns can be classified as follows:
Temporal data will be used again soon
Spatial data will be used in adjacent locations, for example,
same cache line
Non-temporal data which is referenced once and not reused in the
immediate future; for example, some multimedia data
types, such as the vertex buffer in a 3D graphics
application.
These data characteristics are used in the discussions that follow.
Prefetch
This section discusses the mechanics of the software prefetch
instructions. In general, software prefetch instructions should be used to
supplement the practice of tuning a access pattern to suit the automatic
hardware prefetch mechanism.
Software Data Prefetch
The prefetch instruction can hide the latency of data access in
performance-critical sections of application code by allowing data to be
fetched in advance of its actual usage. The
prefetch instructions do not
change the user-visible semantics of a program, although they may
affect the program’s performance. The
prefetch instructions merely
provide a hint to the hardware and generally will not generate
exceptions or faults.
The prefetch instructions load either non-temporal data or temporal
data in the specified cache level. This data access type and the cache
level are specified as a hint. Depending on the implementation, the
instruction fetches 32 or more aligned bytes, including the specified
address byte, into the instruction-specified cache levels.