Intel ARCHITECTURE IA-32 - Manual (Page 498)

IA-32 Intel® Architecture Optimization
B-44
SSE Input
Assists The number of
occurrences of
SSE/SSE2
floating-point
operations needing
assistance to handle
an exception
condition. The
number of
occurrences includes
speculative counts. SSE_input_assist ALL
Packed SP
Retired
3
Non-bogus packed
single-precision
instructions retired. Execution_event ; set
this execution tag:
Packed_SP_retired
NONBOGUS0
Packed DP
Retired
3
Non-bogus packed
double-precision
instructions retired. Execution_event ; set
this execution tag:
Packed_DP_retired
NONBOGUS0
Scalar SP
Retired
3
Non-bogus scalar
single-precision
instructions retired. Execution_event ; set
this execution tag:
Scalar_SP_retired
NONBOGUS0
Scalar DP
Retired
3
Non-bogus scalar
double-precision
instructions retired. Execution_event ; set
this execution tag:
Scalar_DP_retired
NONBOGUS0
64-bit MMX
Instructions
Retired
3
Non-bogus 64-bit
integer SIMD
instruction (MMX
instructions) retired. Execution_event; set the
following execution tag:
64_bit_MMX_retired
NONBOGUS0
128-bit MMX
Instructions
Retired
3
Non-bogus 128-bit
integer SIMD
instructions retired. Execution_event ; set
this execution tag:
128_bit_MMX_
retired
NONBOGUS0
X87 Retired 4 Non-bogus x87
floating-point
instructions retired. Execution_event ; set
this execution tag:
X87_FP_retired
NONBOGUS0
continued
Table B-1 Pentium 4 Processor Performance Metrics (continued)
Metric Description
Event Name or Metric
Expression Event Mask Value
Required