Intel ARCHITECTURE IA-32 - Manual (Page 238)

IA-32 Intel® Architecture Optimization
4-18
Packed Shuffle Word for 64-bit Registers
The pshuf instruction (see Figure 4-8, Example 4-11) uses the
immediate ( imm8 ) operand to select between the four words in either
two MMX registers or one MMX register and a 64-bit memory location.
Bits 1 and 0 of the immediate value encode the source for destination
word 0 in MMX register (
[15-0] ), and so on as shown in the table:
Bits 7 and 6 encode for word 3 in MMX register ( [63-48] ). Similarly,
the 2-bit encoding represents which source word is used, for example,
binary encoding of 10 indicates that source word 2 in MMX
register/memory (
mm / mem[47-32] ) is used, see Figure 4-8 and
Example 4-11.
Bits Word
1 - 0 0
3 - 2 1
5 - 4 2
7 - 6 3
Figure 4-8 pshuf Instruction Example
O M15166
M M /m 64
0 63
X4 X3 X2 X1
M M
0 63
X1 X2 X3 X4