Intel ARCHITECTURE IA-32 - Manual (Page 465)

Using Performance Monitoring Events
B
B-11
Core references are nominally 64 bytes, the size of a 1st-level cache
line. Smaller sizes are called partials, e.g., uncacheable and write
combining reads, uncacheable, write-through and write-protect writes,
and all I/O. Writeback locks, streaming stores and write combining
stores may be full line or partials. Partials are not relevant for cache
references, since they are associated with non-cached data. Likewise,
writebacks (due to the eviction of dirty data) and RFOs (reads for
ownership due to program stores) are not relevant for non-cached data.
The granularity at which the core references are counted by different
bus and memory metrics listed in Table B-1 varies, depending on the
underlying performance-monitoring events that these bus and memory
metrics are derived from. The granularities of core references are listed
below, according to the performance monitoring events that are docu-
mented in Appendix A of the IA-32 Intel® Architecture Software Devel-
oper’s Manual, Volume 3B.
Reads due to program loads
• BSQ_cache_reference: 128 bytes for misses (on current
implementations), 64 bytes for hits
• BSQ_allocation: 128 bytes for hits or misses (on current
implementations), smaller for partials' hits or misses
• BSQ_active_entries: 64 bytes for hits or misses, smaller for partials'
hits or misses
• IOQ_allocation, IOQ_active_entries: 64 bytes, smaller for partials'
hits or misses
Reads due to program writes (RFOs)
• BSQ_cache_reference: 64 bytes for hits or misses
• BSQ_allocation: 64 bytes for hits or misses (the granularity for
misses may change in future implementations of BSQ_allocation),
smaller for partials' hits or misses
• BSQ_active_entries: 64 bytes for hits or misses, smaller for partials'
hits or misses