Intel ARCHITECTURE IA-32 User Manual
Page 528
IA-32 Intel® Architecture Optimization
C-14
Table C-5
Streaming SIMD Extension 64-bit Integer Instructions
Instruction
Latency
1
Throughput
Execution Unit
CPUID
0F3n
0F2n
0x69n
0F3n
0F2n
0x69n 0F2n
PAVGB/PAVGW mm, mm
2
2
1
1
MMX_ALU
PEXTRW r32, mm, imm8
7
7
2
2
2
1
MMX_SHFT,
FP_MISC
PINSRW mm, r32, imm8
4
4
1
1
1
1
MMX_SHFT,
MMX_MISC
PMAX mm, mm
2
2
1
1
MMX_ALU
PMIN mm, mm
2
2
1
1
MMX_ALU
PMOVMSKB
3
r32, mm
7
7
1
2
2
1
FP_MISC
PMULHUW
3
mm, mm
9
8
1
1
FP_MUL
PSADBW mm, mm
4
4
5
1
1
2
MMX_ALU
PSHUFW mm, mm, imm8
2
2
1
1
1
1
MMX_SHFT
Table C-6
MMX Technology 64-bit Instructions
Instruction
Latency
1
Throughput
Execution Unit
2
CPUID
0F3n
0F2n
0x69n
0f3n
0F2n
0x69n
0F2n
MOVD mm, r32
2
2
1
1
MMX_ALU
MOVD
3
r32, mm
5
5
1
1
FP_MISC
MOVQ mm, mm
6
6
1
1
FP_MOV
PACKSSWB/PACKSSD
W/PACKUSWB mm, mm
2
2
1
1
MMX_SHFT
PADDB/PADDW/PADDD
mm, mm
2
2
1
1
MMX_ALU
PADDSB/PADDSW
/PADDUSB/PADDUSW
mm, mm
2
2
1
1
MMX_ALU
PAND mm, mm
2
2
1
1
MMX_ALU
PANDN mm, mm
2
2
1
1
MMX_ALU
PCMPEQB/PCMPEQD
PCMPEQW mm, mm
2
2
1
1
MMX_ALU
continued