Intel ARCHITECTURE IA-32 - Manual (Page 334)

IA-32 Intel® Architecture Optimization
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a line burst transaction. To achieve the best possible performance, it is
recommended to align data along the cache line boundary and write
them consecutively in a cache line size while using non-temporal stores.
If the consecutive writes are prohibitive due to programming
constraints, then software write-combining (
SWWC ) buffers can be used
to enable line burst transaction.
You can declare small SWWC buffers (a cache line for each buffer) in your
application to enable explicit write-combining operations. Instead of
writing to non-temporal memory space immediately, the program writes
data into
SWWC buffers and combines them inside these buffers. The
program only writes a SWWC buffer out using non-temporal stores when
the buffer is filled up, that is, a cache line (128 bytes for the Pentium 4
processor). Although the
SWWC method requires explicit instructions for
performing temporary writes and reads, this ensures that the transaction
on the front-side bus causes line transaction rather than several partial
transactions. Application performance gains considerably from
implementing this technique. These SWWC buffers can be maintained
in the second-level and re-used throughout the program.
Cache Management
The streaming instructions ( prefetch and stores ) can be used to
manage data and minimize disturbance of temporal data held within the
processor’s caches.
In addition, the Pentium 4 processor takes advantage of the Intel C ++
Compiler that supports C ++ language-level features for the Streaming
SIMD Extensions. The Streaming SIMD Extensions and MMX
technology instructions provide intrinsics that allow you to optimize
cache utilization. The examples of such Intel compiler intrinsics are
_mm_prefetch , _mm_stream , _mm_load , _mm_sfence . For more details
on these intrinsics, refer to the Intel C ++ Compiler User’s Guide, order
number 718195.