Intel ARCHITECTURE IA-32 User Manual
Page 522
IA-32 Intel® Architecture Optimization
C-8
PCMPGTB/PCMPGTD/PC
MPGTW xmm, xmm
2
2
1
2
2
1
MMX_ALU
PEXTRW r32, xmm, imm8
7
7
3
2
2
2
MMX_SHFT,
FP_MISC
PINSRW xmm, r32, imm8
4
4
1+1
2
2
2
MMX_SHFT,
MMX_MISC
PMADDWD xmm, xmm
9
8
3+1
2
2
2
FP_MUL
PMAX xmm, xmm
2
2
2
2
MMX_ALU
PMIN xmm, xmm
2
2
2
2
MMX_ALU
PMOVMSKB
3
r32, xmm
7
7
2
2
FP_MISC
PMULHUW/PMULHW/
PMULLW
3
xmm, xmm
9
8
3+1
2
2
2
FP_MUL
PMULUDQ mm, mm
9
8
6
1
2
FP_MUL
PMULUDQ xmm, xmm
9
8
6+2
2
2
4
FP_MUL
POR xmm, xmm
2
2
1
2
2
1
MMX_ALU
PSADBW xmm, xmm
4
4
5+2
2
2
4
MMX_ALU
PSHUFD xmm, xmm, imm8
4
4
2+1
2
2
2
MMX_SHFT
PSHUFHW xmm, xmm,
imm8
2
2
1
2
2
1
MMX_SHFT
PSHUFLW xmm, xmm,
imm8
2
2
1
2
2
1
MMX_SHFT
PSLLDQ xmm, imm8
4
4
4
2
2
4
MMX_SHFT
PSLLW/PSLLD/PSLLQ
xmm, xmm/imm8
2
2
1+1
2
2
2
MMX_SHFT
PSRAW/PSRAD xmm,
xmm/imm8
2
2
1+1
2
2
2
MMX_SHFT
PSRLDQ xmm, imm8
4
4
4
2
2
4
MMX_SHFT
PSRLW/PSRLD/PSRLQ
xmm, xmm/imm8
2
2
1+1
2
2
2
MMX_SHFT
continued
Table C-2
Streaming SIMD Extension 2 128-bit Integer Instructions (continued)
Instruction
Latency
1
Throughput
Execution
Unit
2