Intel ARCHITECTURE IA-32 - Manual (Page 506)

IA-32 Intel® Architecture Optimization
B-52
Branching Metrics Branches Retired
Tagged Mispredicted Branches Retired
Mispredicted Branches Retired
All returns
All indirect branches
All calls
All conditionals
Mispredicted returns
Mispredicted indirect branches
Mispredicted calls
Mispredicted conditionals
TC and Front End Metrics Trace Cache Misses
ITLB Misses
TC to ROM Transfers
TC Flushes
Speculative TC-Built Uops
Speculative TC-Delivered Uops
Speculative Microcode Uops
continued
Table B-6 Metrics That Support Qualification by Logical Processor and
Parallel Counting (continued)