Intel ARCHITECTURE IA-32 - Manual (Page 306)

IA-32 Intel® Architecture Optimization
6-16
The degree to which a consumer of data knows that the data is
weakly-ordered can vary for these cases. As a result, the
sfence
instruction should be used to ensure ordering between routines that
produce weakly-ordered data and routines that consume this data. The
sfence instruction provides a performance-efficient way by ensuring
the ordering when every store instruction that precedes the store
fence instruction in program order is globally visible before any store
instruction which follows the fence .
The lfence Instruction
The lfence ( load fence ) instruction makes it possible for every load
instruction that precedes the lfence instruction in program order to be
globally visible before any load instruction that follows the lfence .
The lfence instruction provides a means of segregating certain load
instructions from other loads.
The mfence Instruction
The mfence ( memory fence ) instruction makes it possible for every
load and store instruction that precedes the mfence instruction in
program order to be globally visible before any other load or store
instruction that follows the mfence . The mfence instruction provides a
means of segregating certain memory instructions from other memory
references.
Note that the use of a lfence and sfence is not equivalent to the use
of a mfence since the load and store fences are not ordered with respect
to each other. In other words, the load fence can be executed before
prior stores, and the store fence can be executed before prior loads. The
mfence instruction should be used whenever the cache line flush
instruction ( clflush ) is used to ensure that speculative memory
references generated by the processor do not interfere with the flush; see
“The clflush Instruction” for more information.