Intel ARCHITECTURE IA-32 User Manual
Page 532
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IA-32 Intel® Architecture Optimization
C-18
Jcc
7
Not
Appli-
cable
0.5
ALU
LOOP
8
1.5
ALU
MOV
1
0.5
0.5
0.5
ALU
MOVSB/MOVSW 1
0.5
0.5
0.5
ALU
MOVZB/MOVZW 1
0.5
0.5
0.5
ALU
NEG/NOT/NOP
1
0.5
0.5
0.5
ALU
POP r32
1.5
1
MEM_LOAD,
ALU
PUSH
1.5
1
MEM_STORE,
ALU
RCL/RCR reg, 1
8
6
4
1
1
ROL/ROR
1
4
0.5
1
RET
8
1
MEM_LOAD,
ALU
SAHF
1
0.5
0.5
0.5
ALU
SAL/SAR/SHL/SHR
1
4
1
0.5
1
SCAS
4
1.5
ALU,MEM_
LOAD
SETcc
5
1.5
ALU
STI
36
STOSB
5
2
ALU,MEM_
STORE
XCHG
1.5
1.5
1
1
ALU
CALL
5
1
ALU,MEM_
STORE
MUL
10
14-18
1
5
DIV
66-80
56-70
30
23
Table C-8
IA-32 General Purpose Instructions (continued)
Instruction
Latency
1
Throughput
Execution Unit
2
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