Agilent Technologies E3632A - Manual (Page 111)

Chapter 4 Remote Interface Reference
Status Reporting Commands
108
Status Reporting Commands
See diagram ‘‘SCPI Status System’’, on page 101 in this chapter for detailed
information of the status register structure of the power supply.
SYSTem:ERRor?
This query command reads one error from the error queue . When the front-
panel
ERROR
annunciator turns on, one or more command syntax or hardware
errors have been detected. A record of up to 20 errors can be stored in the
power supply’s error queue. See ‘‘Error Messages’’ for a complete listing of the
errors in chapter 5.
• Errors are retrieved in first-in-first-out(FIFO) order. The first error returned
is the first error that was stored. When you have read all errors from the
queue, the
ERROR
annunciator turns off. The power supply beeps once each
time an error is generated.
• If more than 20 errors have occurred, the last error stored in the queue (the
most recent error) is replaced with -350 , ‘‘ Too many errors ’’. No additional
errors are stored until you remove errors from the queue. If no errors have
occurred when you read the error queue, the power supply responds with
+0 , ‘‘ No error ’’.
• The error queue is cleared when power has been off or after a
*CLS
(clear
status) command has been executed. The
*RST
(reset) command does not
clear the error queue.
STATus:QUEStionable:CONDition?
This command queries the Questionable Status condition register to check CV
or CC mode of the power supply. The power supply returns a decimal value
which corresponds to the binary-weighted sum of all bits in the register. These
bits are not latched. If ‘‘0’’ is returned, the power supply is in output off or
unregulated state. If ‘‘1’’ is returned, the power supply is in the CC operating
mode and if ‘‘2’’ is returned, the power supply is in the CV operating mode. If
‘‘3’’ is returned, the power supply is in failure.
STATus:QUEStionable?
This command queries the Questionable Status event register. The power
supply returns a decimal value which corresponds to the binary-weighted sum
of all bits in the register. These bits are latched. Reading the event register
clears it.