Document Outline

• Intel® IXP2800 Network Processor
  • Copyright
  • Contents
  • Introduction 1
    • 1.1 About This Document
    • 1.2 Related Documentation
    • 1.3 Terminology
  • Technical Description 2
    • 2.1 Overview
    • 2.2 Intel XScale® Core Microarchitecture
      • 2.2.1 ARM* Compatibility
      • 2.2.2 Features
        • 2.2.2.1 Multiply/Accumulate (MAC)
        • 2.2.2.2 Memory Management
        • 2.2.2.3 Instruction Cache
        • 2.2.2.4 Branch Target Buffer
        • 2.2.2.5 Data Cache
        • 2.2.2.6 Interrupt Controller
        • 2.2.2.7 Address Map
    • 2.3 Microengines
      • 2.3.1 Microengine Bus Arrangement
      • 2.3.2 Control Store
      • 2.3.3 Contexts
      • 2.3.4 Datapath Registers
        • 2.3.4.1 General-Purpose Registers (GPRs)
        • 2.3.4.2 Transfer Registers
        • 2.3.4.3 Next Neighbor Registers
        • 2.3.4.4 Local Memory
      • 2.3.5 Addressing Modes
        • 2.3.5.1 Context-Relative Addressing Mode
        • 2.3.5.2 Absolute Addressing Mode
        • 2.3.5.3 Indexed Addressing Mode
      • 2.3.6 Local CSRs
      • 2.3.7 Execution Datapath
        • 2.3.7.1 Byte Align
        • 2.3.7.2 CAM
      • 2.3.8 CRC Unit
      • 2.3.9 Event Signals
    • 2.4 DRAM
      • 2.4.1 Size Configuration
      • 2.4.2 Read and Write Access
    • 2.5 SRAM
      • 2.5.1 QDR Clocking Scheme
      • 2.5.2 SRAM Controller Configurations
      • 2.5.3 SRAM Atomic Operations
      • 2.5.4 Queue Data Structure Commands
      • 2.5.5 Reference Ordering
        • 2.5.5.1 Reference Order Tables
        • 2.5.5.2 Microengine Software Restrictions to Maintain Ordering
    • 2.6 Scratchpad Memory
      • 2.6.1 Scratchpad Atomic Operations
      • 2.6.2 Ring Commands
    • 2.7 Media and Switch Fabric Interface
      • 2.7.1 SPI-4
      • 2.7.2 CSIX
      • 2.7.3 Receive
        • 2.7.3.1 RBUF
          • 2.7.3.1.1 SPI-4 and the RBUF
          • 2.7.3.1.2 CSIX and RBUF
        • 2.7.3.2 Full Element List
        • 2.7.3.3 RX_THREAD_FREELIST
        • 2.7.3.4 Receive Operation Summary
      • 2.7.4 Transmit
        • 2.7.4.1 TBUF
          • 2.7.4.1.1 SPI-4 and TBUF
          • 2.7.4.1.2 CSIX and TBUF
        • 2.7.4.2 Transmit Operation Summary
      • 2.7.5 The Flow Control Interface
        • 2.7.5.1 SPI-4
        • 2.7.5.2 CSIX
    • 2.8 Hash Unit
    • 2.9 PCI Controller
      • 2.9.1 Target Access
      • 2.9.2 Master Access
      • 2.9.3 DMA Channels
        • 2.9.3.1 DMA Descriptor
        • 2.9.3.2 DMA Channel Operation
        • 2.9.3.3 DMA Channel End Operation
        • 2.9.3.4 Adding Descriptors to an Unterminated Chain
      • 2.9.4 Mailbox and Message Registers
      • 2.9.5 PCI Arbiter
    • 2.10 Control and Status Register Access Proxy
    • 2.11 Intel XScale® Core Peripherals
      • 2.11.1 Interrupt Controller
      • 2.11.2 Timers
      • 2.11.3 General Purpose I/O
      • 2.11.4 Universal Asynchronous Receiver/Transmitter
      • 2.11.5 Slowport
    • 2.12 I/O Latency
    • 2.13 Performance Monitor
  • Intel XScale® Core 3
    • 3.1 Introduction
    • 3.2 Features
      • 3.2.1 Multiply/ACcumulate (MAC)
      • 3.2.2 Memory Management
      • 3.2.3 Instruction Cache
      • 3.2.4 Branch Target Buffer (BTB)
      • 3.2.5 Data Cache
      • 3.2.6 Performance Monitoring
      • 3.2.7 Power Management
      • 3.2.8 Debugging
      • 3.2.9 JTAG
    • 3.3 Memory Management
      • 3.3.1 Architecture Model
        • 3.3.1.1 Version 4 versus Version 5
        • 3.3.1.2 Memory Attributes
          • 3.3.1.2.1 Page (P) Attribute Bit
          • 3.3.1.2.2 Instruction Cache
          • 3.3.1.2.3 Data Cache and Write Buffer
          • 3.3.1.2.4 Details on Data Cache and Write Buffer Behavior
          • 3.3.1.2.5 Memory Operation Ordering
      • 3.3.2 Exceptions
      • 3.3.3 Interaction of the MMU, Instruction Cache, and Data Cache
      • 3.3.4 Control
        • 3.3.4.1 Invalidate (Flush) Operation
        • 3.3.4.2 Enabling/Disabling
        • 3.3.4.3 Locking Entries
        • 3.3.4.4 Round-Robin Replacement Algorithm
    • 3.4 Instruction Cache
      • 3.4.1 Instruction Cache Operation
        • 3.4.1.1 Operation when Instruction Cache is Enabled
        • 3.4.1.2 Operation when Instruction Cache is Disabled
        • 3.4.1.3 Fetch Policy
        • 3.4.1.4 Round-Robin Replacement Algorithm
        • 3.4.1.5 Parity Protection
        • 3.4.1.6 Instruction Cache Coherency
      • 3.4.2 Instruction Cache Control
        • 3.4.2.1 Instruction Cache State at Reset
        • 3.4.2.2 Enabling/Disabling
        • 3.4.2.3 Invalidating the Instruction Cache
        • 3.4.2.4 Locking Instructions in the Instruction Cache
        • 3.4.2.5 Unlocking Instructions in the Instruction Cache
    • 3.5 Branch Target Buffer (BTB)
      • 3.5.1 Branch Target Buffer Operation
        • 3.5.1.1 Reset
      • 3.5.2 Update Policy
      • 3.5.3 BTB Control
        • 3.5.3.1 Disabling/Enabling
        • 3.5.3.2 Invalidation
    • 3.6 Data Cache
      • 3.6.1 Overviews
        • 3.6.1.1 Data Cache Overview
        • 3.6.1.2 Mini-Data Cache Overview
        • 3.6.1.3 Write Buffer and Fill Buffer Overview
      • 3.6.2 Data Cache and Mini-Data Cache Operation
        • 3.6.2.1 Operation when Caching is Enabled
        • 3.6.2.2 Operation when Data Caching is Disabled
        • 3.6.2.3 Cache Policies
          • 3.6.2.3.1 Cacheability
          • 3.6.2.3.2 Read Miss Policy
          • 3.6.2.3.3 Write Miss Policy
          • 3.6.2.3.4 Write-Back versus Write-Through
        • 3.6.2.4 Round-Robin Replacement Algorithm
        • 3.6.2.5 Parity Protection
        • 3.6.2.6 Atomic Accesses
      • 3.6.3 Data Cache and Mini-Data Cache Control
        • 3.6.3.1 Data Memory State After Reset
        • 3.6.3.2 Enabling/Disabling
        • 3.6.3.3 Invalidate and Clean Operations
          • 3.6.3.3.1 Global Clean and Invalidate Operation
      • 3.6.4 Reconfiguring the Data Cache as Data RAM
      • 3.6.5 Write Buffer/Fill Buffer Operation and Control
    • 3.7 Configuration
    • 3.8 Performance Monitoring
      • 3.8.1 Performance Monitoring Events
        • 3.8.1.1 Instruction Cache Efficiency Mode
        • 3.8.1.2 Data Cache Efficiency Mode
        • 3.8.1.3 Instruction Fetch Latency Mode
        • 3.8.1.4 Data/Bus Request Buffer Full Mode
        • 3.8.1.5 Stall/Writeback Statistics
        • 3.8.1.6 Instruction TLB Efficiency Mode
        • 3.8.1.7 Data TLB Efficiency Mode
      • 3.8.2 Multiple Performance Monitoring Run Statistics
    • 3.9 Performance Considerations
      • 3.9.1 Interrupt Latency
      • 3.9.2 Branch Prediction
      • 3.9.3 Addressing Modes
      • 3.9.4 Instruction Latencies
        • 3.9.4.1 Performance Terms
        • 3.9.4.2 Branch Instruction Timings
        • 3.9.4.3 Data Processing Instruction Timings
        • 3.9.4.4 Multiply Instruction Timings
        • 3.9.4.5 Saturated Arithmetic Instructions
        • 3.9.4.6 Status Register Access Instructions
        • 3.9.4.7 Load/Store Instructions
        • 3.9.4.8 Semaphore Instructions
        • 3.9.4.9 Coprocessor Instructions
        • 3.9.4.10 Miscellaneous Instruction Timing
        • 3.9.4.11 Thumb Instructions
    • 3.10 Test Features
      • 3.10.1 IXP2800 Network Processor Endianness
        • 3.10.1.1 Read and Write Transactions Initiated by the Intel XScale® Core
          • 3.10.1.1.1 Reads Initiated by the Intel XScale® Core
          • 3.10.1.1.2 The Intel XScale® Core Writing to the IXP2800 Network Processor
    • 3.11 Intel XScale® Core Gasket Unit
      • 3.11.1 Overview
      • 3.11.2 Intel XScale® Core Gasket Functional Description
        • 3.11.2.1 Command Memory Bus to Command Push/Pull Conversion
      • 3.11.3 CAM Operation
      • 3.11.4 Atomic Operations
        • 3.11.4.1 Summary of Rules for the Atomic Command Regarding I/O
        • 3.11.4.2 Intel XScale® Core Access to SRAM Q-Array
      • 3.11.5 I/O Transaction
      • 3.11.6 Hash Access
      • 3.11.7 Gasket Local CSR
      • 3.11.8 Interrupt
    • 3.12 Intel XScale® Core Peripheral Interface
      • 3.12.1 XPI Overview
        • 3.12.1.1 Data Transfers
        • 3.12.1.2 Data Alignment
        • 3.12.1.3 Address Spaces for XPI Internal Devices
      • 3.12.2 UART Overview
      • 3.12.3 UART Operation
        • 3.12.3.1 UART FIFO OPERATION
          • 3.12.3.1.1 UART FIFO Interrupt Mode Operation - Receiver Interrupt
          • 3.12.3.1.2 FIFO Polled Mode Operation
      • 3.12.4 Baud Rate Generator
      • 3.12.5 General Purpose I/O (GPIO)
      • 3.12.6 Timers
        • 3.12.6.1 Timer Operation
      • 3.12.7 Slowport Unit
        • 3.12.7.1 PROM Device Support
        • 3.12.7.2 Microprocessor Interface Support for the Framer
        • 3.12.7.3 Slowport Unit Interfaces
        • 3.12.7.4 Address Space
        • 3.12.7.5 Slowport Interfacing Topology
        • 3.12.7.6 Slowport 8-Bit Device Bus Protocols
          • 3.12.7.6.1 Mode 0 Single Write Transfer for Fixed-Timed Device
          • 3.12.7.6.2 Mode 0 Single Write Transfer for Self-Timing Device
          • 3.12.7.6.3 Mode 0 Single Read Transfer for Fixed-Timed Device
          • 3.12.7.6.4 Single Read Transfer for a Self-Timing Device
        • 3.12.7.7 SONET/SDH Microprocessor Access Support
          • 3.12.7.7.1 Mode 1: 16-Bit Microprocessor Interface Support with 16-Bit Address Lines
          • 3.12.7.7.2 Mode 2: Interface with 8 Data Bits and 11 Address Bits
          • 3.12.7.7.3 Mode 3: Support for the Intel and AMCC* 2488 Mbps SONET/SDH Microprocessor Interface
  • Microengines 4
    • 4.1 Overview
      • 4.1.1 Control Store
      • 4.1.2 Contexts
      • 4.1.3 Datapath Registers
        • 4.1.3.1 General-Purpose Registers (GPRs)
        • 4.1.3.2 Transfer Registers
        • 4.1.3.3 Next Neighbor Registers
        • 4.1.3.4 Local Memory
      • 4.1.4 Addressing Modes
        • 4.1.4.1 Context-Relative Addressing Mode
        • 4.1.4.2 Absolute Addressing Mode
        • 4.1.4.3 Indexed Addressing Mode
    • 4.2 Local CSRs
    • 4.3 Execution Datapath
      • 4.3.1 Byte Align
      • 4.3.2 CAM
    • 4.4 CRC Unit
    • 4.5 Event Signals
      • 4.5.1 Microengine Endianness
        • 4.5.1.1 Read from RBUF (64 Bits)
        • 4.5.1.2 Write to TBUF
        • 4.5.1.3 Read/Write from/to SRAM
        • 4.5.1.4 Read/Write from/to DRAM
        • 4.5.1.5 Read/Write from/to SHaC and Other CSRs
        • 4.5.1.6 Write to Hash Unit
      • 4.5.2 Media Access
        • 4.5.2.1 Read from RBUF
        • 4.5.2.2 Write to TBUF
        • 4.5.2.3 TBUF to SPI-4 Transfer
  • DRAM 5
    • 5.1 Overview
    • 5.2 Size Configuration
    • 5.3 DRAM Clocking
    • 5.4 Bank Policy
    • 5.5 Interleaving
      • 5.5.1 Three Channels Active (3-Way Interleave)
      • 5.5.2 Two Channels Active (2-Way Interleave)
      • 5.5.3 One Channel Active (No Interleave)
      • 5.5.4 Interleaving Across RDRAMs and Banks
    • 5.6 Parity and ECC
      • 5.6.1 Parity and ECC Disabled
      • 5.6.2 Parity Enabled
      • 5.6.3 ECC Enabled
      • 5.6.4 ECC Calculation and Syndrome
    • 5.7 Timing Configuration
    • 5.8 Microengine Signals
    • 5.9 Serial Port
    • 5.10 RDRAM Controller Block Diagram
      • 5.10.1 Commands
      • 5.10.2 DRAM Write
        • 5.10.2.1 Masked Write
      • 5.10.3 DRAM Read
      • 5.10.4 CSR Write
      • 5.10.5 CSR Read
      • 5.10.6 Arbitration
      • 5.10.7 Reference Ordering
    • 5.11 DRAM Push/Pull Arbiter
      • 5.11.1 Arbiter Push/Pull Operation
      • 5.11.2 DRAM Push Arbiter Description
    • 5.12 DRAM Pull Arbiter Description
  • SRAM Interface 6
    • 6.1 Overview
    • 6.2 SRAM Interface Configurations
      • 6.2.1 Internal Interface
      • 6.2.2 Number of Channels
      • 6.2.3 Coprocessor and/or SRAMs Attached to a Channel
    • 6.3 SRAM Controller Configurations
    • 6.4 Command Overview
      • 6.4.1 Basic Read/Write Commands
      • 6.4.2 Atomic Operations
      • 6.4.3 Queue Data Structure Commands
        • 6.4.3.1 Read_Q_Descriptor Commands
        • 6.4.3.2 Write_Q_Descriptor Commands
        • 6.4.3.3 ENQ and DEQ Commands
      • 6.4.4 Ring Data Structure Commands
      • 6.4.5 Journaling Commands
      • 6.4.6 CSR Accesses
    • 6.5 Parity
    • 6.6 Address Map
    • 6.7 Reference Ordering
      • 6.7.1 Reference Order Tables
      • 6.7.2 Microcode Restrictions to Maintain Ordering
    • 6.8 Coprocessor Mode
  • SHaC - Unit Expansion 7
    • 7.1 Overview
      • 7.1.1 SHaC Unit Block Diagram
      • 7.1.2 Scratchpad
        • 7.1.2.1 Scratchpad Description
        • 7.1.2.2 Scratchpad Interface
          • 7.1.2.2.1 Command Interface
          • 7.1.2.2.2 Push/Pull Interface
          • 7.1.2.2.3 CSR Bus Interface
          • 7.1.2.2.4 Advanced Peripherals Bus Interface (APB)
        • 7.1.2.3 Scratchpad Block Level Diagram
          • 7.1.2.3.1 Scratchpad Commands
          • 7.1.2.3.2 Ring Commands
          • 7.1.2.3.3 Clocks and Reset
          • 7.1.2.3.4 Reset Registers
      • 7.1.3 Hash Unit
        • 7.1.3.1 Hashing Operation
        • 7.1.3.2 Hash Algorithm
  • Media and Switch Fabric Interface 8
    • 8.1 Overview
      • 8.1.1 SPI-4
      • 8.1.2 CSIX
      • 8.1.3 CSIX/SPI-4 Interleave Mode
    • 8.2 Receive
      • 8.2.1 Receive Pins
      • 8.2.2 RBUF
        • 8.2.2.1 SPI-4
        • 8.2.2.2 CSIX
      • 8.2.3 Full Element List
      • 8.2.4 Rx_Thread_Freelist_#
      • 8.2.5 Rx_Thread_Freelist_Timeout_#
      • 8.2.6 Receive Operation Summary
      • 8.2.7 Receive Flow Control Status
        • 8.2.7.1 SPI-4
        • 8.2.7.2 CSIX
          • 8.2.7.2.1 Link-Level
          • 8.2.7.2.2 Virtual Output Queue
      • 8.2.8 Parity
        • 8.2.8.1 SPI-4
        • 8.2.8.2 CSIX
          • 8.2.8.2.1 Horizontal Parity
          • 8.2.8.2.2 Vertical Parity
      • 8.2.9 Error Cases
    • 8.3 Transmit
      • 8.3.1 Transmit Pins
      • 8.3.2 TBUF
        • 8.3.2.1 SPI-4
        • 8.3.2.2 CSIX
      • 8.3.3 Transmit Operation Summary
        • 8.3.3.1 SPI-4
        • 8.3.3.2 CSIX
        • 8.3.3.3 Transmit Summary
      • 8.3.4 Transmit Flow Control Status
        • 8.3.4.1 SPI-4
        • 8.3.4.2 CSIX
          • 8.3.4.2.1 Link-Level
          • 8.3.4.2.2 Virtual Output Queue
      • 8.3.5 Parity
        • 8.3.5.1 SPI-4
        • 8.3.5.2 CSIX
          • 8.3.5.2.1 Horizontal Parity
          • 8.3.5.2.2 Vertical Parity
    • 8.4 RBUF and TBUF Summary
    • 8.5 CSIX Flow Control Interface
      • 8.5.1 TXCSRB and RXCSRB Signals
      • 8.5.2 FCIFIFO and FCEFIFO Buffers
        • 8.5.2.1 Full Duplex CSIX
        • 8.5.2.2 Simplex CSIX
      • 8.5.3 TXCDAT/RXCDAT, TXCSOF/RXCSOF, TXCPAR/RXCPAR, and TXCFC/RXCFC Signals
    • 8.6 Deskew and Training
      • 8.6.1 Data Training Pattern
      • 8.6.2 Flow Control Training Pattern
      • 8.6.3 Use of Dynamic Training
    • 8.7 CSIX Startup Sequence
      • 8.7.1 CSIX Full Duplex
        • 8.7.1.1 Ingress IXP2800 Network Processor
        • 8.7.1.2 Egress IXP2800 Network Processor
        • 8.7.1.3 Single IXP2800 Network Processor
      • 8.7.2 CSIX Simplex
        • 8.7.2.1 Ingress IXP2800 Network Processor
        • 8.7.2.2 Egress IXP2800 Network Processor
        • 8.7.2.3 Single IXP2800 Network Processor
    • 8.8 Interface to Command and Push and Pull Buses
      • 8.8.1 RBUF or MSF CSR to Microengine S_TRANSFER_IN Register for Instruction:
      • 8.8.2 Microengine S_TRANSFER_OUT Register to TBUF or MSF CSR for Instruction:
      • 8.8.3 Microengine to MSF CSR for Instruction:
      • 8.8.4 From RBUF to DRAM for Instruction:
      • 8.8.5 From DRAM to TBUF for Instruction:
    • 8.9 Receiver and Transmitter Interoperation with Framers and Switch Fabrics
      • 8.9.1 Receiver and Transmitter Configurations
        • 8.9.1.1 Simplex Configuration
        • 8.9.1.2 Hybrid Simplex Configuration
        • 8.9.1.3 Dual Network Processor Full Duplex Configuration
        • 8.9.1.4 Single Network Processor Full Duplex Configuration (SPI-4.2)
        • 8.9.1.5 Single Network Processor, Full Duplex Configuration (SPI-4.2 and CSIX-L1)
      • 8.9.2 System Configurations
        • 8.9.2.1 Framer, Single Network Processor Ingress and Egress, and Fabric Interface Chip
        • 8.9.2.2 Framer, Dual Network Processor Ingress, Single Network Processor Egress, and Fabric Interface Chip
        • 8.9.2.3 Framer, Single Network Processor Ingress and Egress, and CSIX-L1 Chips for Translation and Fabric Interface
        • 8.9.2.4 CPU Complex, Network Processor, and Fabric Interface Chip
        • 8.9.2.5 Framer, Single Network Processor, Co-Processor, and Fabric Interface Chip
      • 8.9.3 SPI-4.2 Support
        • 8.9.3.1 SPI-4.2 Receiver
        • 8.9.3.2 SPI-4.2 Transmitter
      • 8.9.4 CSIX-L1 Protocol Support
        • 8.9.4.1 CSIX-L1 Interface Reference Model: Traffic Manager and Fabric Interface Chip
        • 8.9.4.2 Intel® IXP2800 Support of the CSIX-L1 Protocol
          • 8.9.4.2.1 Mapping to 16-Bit Wide DDR LVDS
          • 8.9.4.2.2 Support for Dual Chip, Full-Duplex Operation
          • 8.9.4.2.3 Support for Simplex Operation
          • 8.9.4.2.4 Support for Hybrid Simplex Operation
          • 8.9.4.2.5 Support for Dynamic De-Skew Training
        • 8.9.4.3 CSIX-L1 Protocol Receiver Support
        • 8.9.4.4 CSIX-L1 Protocol Transmitter Support
        • 8.9.4.5 Implementation of a Bridge Chip to CSIX-L1
      • 8.9.5 Dual Protocol (SPI and CSIX-L1) Support
        • 8.9.5.1 Dual Protocol Receiver Support
        • 8.9.5.2 Dual Protocol Transmitter Support
        • 8.9.5.3 Implementation of a Bridge Chip to CSIX-L1 and SPI-4.2
      • 8.9.6 Transmit State Machine
        • 8.9.6.1 SPI-4.2 Transmitter State Machine
        • 8.9.6.2 Training Transmitter State Machine
        • 8.9.6.3 CSIX-L1 Transmitter State Machine
      • 8.9.7 Dynamic De-Skew
      • 8.9.8 Summary of Receiver and Transmitter Signals
  • PCI Unit 9
    • 9.1 Overview
    • 9.2 PCI Pin Protocol Interface Block
      • 9.2.1 PCI Commands
      • 9.2.2 IXP2800 Network Processor Initialization
        • 9.2.2.1 Initialization by the Intel XScale® Core
        • 9.2.2.2 Initialization by a PCI Host
      • 9.2.3 PCI Type 0 Configuration Cycles
        • 9.2.3.1 Configuration Write
        • 9.2.3.2 Configuration Read
      • 9.2.4 PCI 64-Bit Bus Extension
      • 9.2.5 PCI Target Cycles
        • 9.2.5.1 PCI Accesses to CSR
        • 9.2.5.2 PCI Accesses to DRAM
        • 9.2.5.3 PCI Accesses to SRAM
        • 9.2.5.4 Target Write Accesses from the PCI Bus
        • 9.2.5.5 Target Read Accesses from the PCI Bus
      • 9.2.6 PCI Initiator Transactions
        • 9.2.6.1 PCI Request Operation
        • 9.2.6.2 PCI Commands
        • 9.2.6.3 Initiator Write Transactions
        • 9.2.6.4 Initiator Read Transactions
        • 9.2.6.5 Initiator Latency Timer
        • 9.2.6.6 Special Cycle
      • 9.2.7 PCI Fast Back-to-Back Cycles
      • 9.2.8 PCI Retry
      • 9.2.9 PCI Disconnect
      • 9.2.10 PCI Built-In System Test
      • 9.2.11 PCI Central Functions
        • 9.2.11.1 PCI Interrupt Inputs
        • 9.2.11.2 PCI Reset Output
        • 9.2.11.3 PCI Internal Arbiter
    • 9.3 Slave Interface Block
      • 9.3.1 CSR Interface
      • 9.3.2 SRAM Interface
        • 9.3.2.1 SRAM Slave Writes
        • 9.3.2.2 SRAM Slave Reads
      • 9.3.3 DRAM Interface
        • 9.3.3.1 DRAM Slave Writes
        • 9.3.3.2 DRAM Slave Reads
      • 9.3.4 Mailbox and Doorbell Registers
      • 9.3.5 PCI Interrupt Pin
    • 9.4 Master Interface Block
      • 9.4.1 DMA Interface
        • 9.4.1.1 Allocation of the DMA Channels
        • 9.4.1.2 Special Registers for Microengine Channels
        • 9.4.1.3 DMA Descriptor
        • 9.4.1.4 DMA Channel Operation
        • 9.4.1.5 DMA Channel End Operation
        • 9.4.1.6 Adding Descriptor to an Unterminated Chain
        • 9.4.1.7 DRAM to PCI Transfer
        • 9.4.1.8 PCI to DRAM Transfer
      • 9.4.2 Push/Pull Command Bus Target Interface
        • 9.4.2.1 Command Bus Master Access to Local Configuration Registers
        • 9.4.2.2 Command Bus Master Access to Local Control and Status Registers
        • 9.4.2.3 Command Bus Master Direct Access to PCI Bus
          • 9.4.2.3.1 PCI Address Generation for IO and MEM Cycles
          • 9.4.2.3.2 PCI Address Generation for Configuration Cycles
          • 9.4.2.3.3 PCI Address Generation for Special and IACK Cycles
          • 9.4.2.3.4 PCI Enables
          • 9.4.2.3.5 PCI Command
    • 9.5 PCI Unit Error Behavior
      • 9.5.1 PCI Target Error Behavior
        • 9.5.1.1 Target Access Has an Address Parity Error
        • 9.5.1.2 Initiator Asserts PCI_PERR_L in Response to One of Our Data Phases
        • 9.5.1.3 Discard Timer Expires on a Target Read
        • 9.5.1.4 Target Access to the PCI_CSR_BAR Space Has Illegal Byte Enables
        • 9.5.1.5 Target Write Access Receives Bad Parity PCI_PAR with the Data
        • 9.5.1.6 SRAM Responds with a Memory Error on One or More Data Phases on a Target Read
        • 9.5.1.7 DRAM Responds with a Memory Error on One or More Data Phases on a Target Read
      • 9.5.2 As a PCI Initiator During a DMA Transfer
        • 9.5.2.1 DMA Read from DRAM (Memory-to-PCI Transaction) Gets a Memory Error
        • 9.5.2.2 DMA Read from SRAM (Descriptor Read) Gets a Memory Error
        • 9.5.2.3 DMA from DRAM Transfer (Write to PCI) Receives PCI_PERR_L on PCI Bus
        • 9.5.2.4 DMA To DRAM (Read from PCI) Has Bad Data Parity
        • 9.5.2.5 DMA Transfer Experiences a Master Abort (Time-Out) on PCI
        • 9.5.2.6 DMA Transfer Receives a Target Abort Response During a Data Phase
        • 9.5.2.7 DMA Descriptor Has a 0x0 Word Count (Not an Error)
      • 9.5.3 As a PCI Initiator During a Direct Access from the Intel XScale® Core or Microengine
        • 9.5.3.1 Master Transfer Experiences a Master Abort (Time-Out) on PCI
        • 9.5.3.2 Master Transfer Receives a Target Abort Response During a Data Phase
        • 9.5.3.3 Master from the Intel XScale® Core or Microengine Transfer (Write to PCI) Receives PCI_PERR_L on PCI Bus
        • 9.5.3.4 Master Read from PCI (Read from PCI) Has Bad Data Parity
        • 9.5.3.5 Master Transfer Receives PCI_SERR_L from the PCI Bus
        • 9.5.3.6 Intel XScale® Core Microengine Requests Direct Transfer when the PCI Bus is in Reset
    • 9.6 PCI Data Byte Lane Alignment
      • 9.6.1 Endian for Byte Enable
  • Clocks and Reset 10
    • 10.1 Clocks
    • 10.2 Synchronization Between Frequency Domains
    • 10.3 Reset
      • 10.3.1 Hardware Reset Using nRESET or PCI_RST_L
      • 10.3.2 PCI-Initiated Reset
      • 10.3.3 Watchdog Timer-Initiated Reset
        • 10.3.3.1 Slave Network Processor (Non-Central Function)
        • 10.3.3.2 Master Network Processor (PCI Host, Central Function)
        • 10.3.3.3 Master Network Processor (Central Function)
      • 10.3.4 Software-Initiated Reset
      • 10.3.5 Reset Removal Operation Based on CFG_PROM_BOOT
        • 10.3.5.1 When CFG_PROM_BOOT is 1 (BOOT_PROM is Present)
        • 10.3.5.2 When CFG_PROM_BOOT is 0 (BOOT_PROM is Not Present)
      • 10.3.6 Strap Pins
      • 10.3.7 Powerup Reset Sequence
    • 10.4 Boot Mode
      • 10.4.1 Flash ROM
      • 10.4.2 PCI Host Download
    • 10.5 Initialization
  • Performance Monitor Unit 11
    • 11.1 Introduction
      • 11.1.1 Motivation for Performance Monitors
      • 11.1.2 Motivation for Choosing CHAP Counters
      • 11.1.3 Functional Overview of CHAP Counters
      • 11.1.4 Basic Operation of the Performance Monitor Unit
      • 11.1.5 Definition of CHAP Terminology
      • 11.1.6 Definition of Clock Domains
    • 11.2 Interface and CSR Description
      • 11.2.1 APB Peripheral
      • 11.2.2 CAP Description
        • 11.2.2.1 Selecting the Access Mode
        • 11.2.2.2 PMU CSR
        • 11.2.2.3 CAP Writes
        • 11.2.2.4 CAP Reads
      • 11.2.3 Configuration Registers
    • 11.3 Performance Measurements
    • 11.4 Events Monitored in Hardware
      • 11.4.1 Queue Statistics Events
        • 11.4.1.1 Queue Latency
        • 11.4.1.2 Queue Utilization
      • 11.4.2 Count Events
        • 11.4.2.1 Hardware Block Execution Count
      • 11.4.3 Design Block Select Definitions
      • 11.4.4 Null Event
      • 11.4.5 Threshold Events
      • 11.4.6 External Input Events
        • 11.4.6.1 XPI Events Target ID(000001) / Design Block #(0100)
        • 11.4.6.2 SHaC Events Target ID(000010) / Design Block #(0101)
        • 11.4.6.3 IXP2800 Network Processor MSF Events Target ID(000011) / Design Block #(0110)
        • 11.4.6.4 Intel XScale® Core Events Target ID(000100) / Design Block #(0111)
        • 11.4.6.5 PCI Events Target ID(000101) / Design Block #(1000)
        • 11.4.6.6 ME00 Events Target ID(100000) / Design Block #(1001)
        • 11.4.6.7 ME01 Events Target ID(100001) / Design Block #(1001)
        • 11.4.6.8 ME02 Events Target ID(100010) / Design Block #(1001)
        • 11.4.6.9 ME03 Events Target ID(100011) / Design Block #(1001)
        • 11.4.6.10 ME04 Events Target ID(100100) / Design Block #(1001)
        • 11.4.6.11 ME05 Events Target ID(100101) / Design Block #(1001)
        • 11.4.6.12 ME06 Events Target ID(100110) / Design Block #(1001)
        • 11.4.6.13 ME07 Events Target ID(100111) / Design Block #(1001)
        • 11.4.6.14 ME10 Events Target ID(110000) / Design Block #(1010)
        • 11.4.6.15 ME11 Events Target ID(110001) / Design Block #(1010)
        • 11.4.6.16 ME12 Events Target ID(110010) / Design Block #(1010)
        • 11.4.6.17 ME13 Events Target ID(110011) / Design Block #(1010)
        • 11.4.6.18 ME14 Events Target ID(110100) / Design Block #(1010)
        • 11.4.6.19 ME15 Events Target ID(110101) / Design Block #(1010)
        • 11.4.6.20 ME16 Events Target ID(100110) / Design Block #(1010)
        • 11.4.6.21 ME17 Events Target ID(110111) / Design Block #(1010)
        • 11.4.6.22 SRAM DP1 Events Target ID(001001) / Design Block #(0010)
        • 11.4.6.23 SRAM DP0 Events Target ID(001010) / Design Block #(0010)
        • 11.4.6.24 SRAM CH3 Events Target ID(001011) / Design Block #(0010)
        • 11.4.6.25 SRAM CH2 Events Target ID(001100) / Design Block #(0010)
        • 11.4.6.26 SRAM CH1 Events Target ID(001101) / Design Block #(0010)
        • 11.4.6.27 SRAM CH0 Events Target ID(001110) / Design Block #(0010)
        • 11.4.6.28 DRAM DPLA Events Target ID(010010) / Design Block #(0011)
        • 11.4.6.29 DRAM DPSA Events Target ID(010011) / Design Block #(0011)
        • 11.4.6.30 IXP2800 Network Processor DRAM CH2 Events Target ID(010100) / Design Block #(0011)
        • 11.4.6.31 IXP2800 Network Processor DRAM CH1 Events Target ID(010101) / Design Block #(0011)
        • 11.4.6.32 IXP2800 Network Processor DRAM CH0 Events Target ID(010110) / Design Block #(0011)