3 single ixp2800 network processor, 2 csix simplex, 1 ingress ixp2800 network processor – Intel NETWORK PROCESSOR IXP2800 User Manual

Page 288: Single ixp2800 network processor, Csix simplex 8.7.2.1, Ingress ixp2800 network processor

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288

Hardware Reference Manual

Intel

®

IXP2800 Network Processor

Media and Switch Fabric Interface

8.7.1.3

Single IXP2800 Network Processor

1. The Microengine or the Intel XScale

®

core writes a 1 to MSF_Tx_Control[Transmit_Idle] and

MSF_Tx_Control[Transmit_Enable] so that Idle CFrames with low CReady and DReady bits

are sent over TDAT.

2. The Microengine or the Intel XScale

®

core writes a 1 to MSF_Rx_Control[RX_En_C] so that

Idle CFrames can be received.

3. The Microengine or the Intel XScale

®

core writes a 0 to

FC_STATUS_OVERRIDE[Ingress_Force_En].

4. The Microengine or the Intel XScale

®

core polls on

MSF_Interrupt_Status[Detected_CSIX_Idle] to see when the first Idle CFrame is received.
The Intel XScale

®

core may use the Detected_CSIX_Idle Interrupt if

MSF_Interrupt_Enable[Detected_CSIX_Idle] is set.

5. When the first Idle CFrame is received, the Microengine or the Intel XScale

®

core writes a 0

to FC_STATUS_OVERRIDE[Egress_Force_En] to deactivate SRB Override or writes 2'b11

to FC_STATUS_OVERRIDE[7:6] ([TM_CReady and TM_DReady]).

6. The Microengine or the Intel XScale

®

core writes a 1 to MSF_Tx_Control[TX_En_CC] and

MSF_Tx_Control[TX_En_CD]. IXP2800 resumes normal operation.

8.7.2

CSIX Simplex

8.7.2.1

Ingress IXP2800 Network Processor

1. On reset, FC_STATUS_OVERRIDE[Egress_Force_En] is set to force Ingress IXP2800 to

send Idle CFrames with low CReady and DReady bits to Switch Fabric over TXCDAT.

2. The Microengine or the Intel XScale

®

core writes a 1 to MSF_Rx_Control[RX_En_C] so that

Idle CFrames can be received.

3. The Microengine or the Intel XScale

®

core polls on

MSF_Interrupt_Status[Detected_CSIX_Idle] to see when the first Idle CFrame is received.

The Intel XScale

®

core may use the Detected_CSIX_Idle Interrupt if

MSF_Interrupt_Enable[Detected_CSIX_Idle] is set.

4. When the first Idle CFrame is received, the Microengine or the Intel XScale

®

core writes a 0

to FC_STATUS_OVERRIDE[Egress_Force_En]. Idle CFrames with “ready bits” high will be

transmitted over TXCDAT. Ingress IXP2800 may resume normal operation.

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