Intel NETWORK PROCESSOR IXP2800 - Manual (Page 287)

Hardware Reference Manual 287
Intel
®
IXP2800 Network Processor
Media and Switch Fabric Interface
8.7 CSIX Startup Sequence
This section defines the sequence required to startup the CSIX interface.
8.7.1 CSIX Full Duplex
8.7.1.1 Ingress IXP2800 Network Processor
1. On reset, FC_STATUS_OVERRIDE[Egress_Force_En] is set to force the Ingress IXP2800 to
send Idle CFrames with low CReady and DReady bits to the Egress IXP2800 over TXCSRB.
2. The Microengine or the Intel XScale ® core writes a 1 to MSF_Rx_Control[RX_En_C] so that
Idle CFrames can be received.
3. The Microengine or the Intel XScale
®
core polls on
MSF_Interrupt_Status[Detected_CSIX_Idle] to see when the first Idle CFrame is received.
The Intel XScale
® core may use the Detected_CSIX_Idle Interrupt if
MSF_Interrupt_Enable[Detected_CSIX_Idle] is set.
4. When the first Idle CFrame is received, the Microengine or the Intel XScale
®
core writes a 0
to FC_STATUS_OVERRIDE[Egress_Force_En] to deactivate SRB Override or writes 2'b11
to FC_STATUS_OVERRIDE[7:6] ([TM_CReady] and [TM_DReady]). This will inform the
Egress IXP2800 that the Switch Fabric has sent an Idle CFrame and the Ingress IXP2800 has
detected it.
8.7.1.2 Egress IXP2800 Network Processor
1. On reset, FC_STATUS_OVERRIDE[Ingress_Force_En] is set.
2. The Microengine or the Intel XScale ® core writes a 1 to MSF_Tx_Control[Transmit_Idle] and
MSF_Tx_Control[Transmit_Enable] so that Idle CFrames with low CReady and Dready bits
are sent over TDAT.
3. The Microengine or the Intel XScale
®
core writes a 0 to
FC_STATUS_OVERRIDE[Ingress_Force_En]. The Egress IXP2800 will then be sending Idle
CFrames with CReady and DReady according to what is received on RXCSRB from the
Ingress IXP2800. If the Egress IXP2800 has not detected an Idle CFrame, low TM_CReady
and TM_DReady bits will be transmitted over its TXCSRB pin. If it has detected an Idle
CFrame, the TM_CReady and TM_DReady bits are high. The TM_CReady and TM_DReady
bits received on RXCSRB by the Ingress IXP2800 are used in the Base Headers of CFrames
transmitted over TDAT.
4. The Microengine or the Intel XScale
®
core polls on FC_Ingress_Status[TM_CReady] and
FC_Ingress_Status[TM_DReady]. When they are seen active, the Microengine or the Intel
XScale
®
core writes a 1 to MSF_Tx_Control[TX_En_CC] and
MSF_Tx_Control[TX_En_CD]. Egress IXP2800 then resumes normal operation. Likewise,
when the Switch Fabric recognizes Idle CFrames with “ready bits” high, it will assume normal
operation.