Intel NETWORK PROCESSOR IXP2800 - Manual (Page 31)

Hardware Reference Manual 31
Intel
®
IXP2800 Network Processor
Technical Description
2.2.2.4 Branch Target Buffer
The Intel XScale ® microarchitecture provides a Branch Target Buffer (BTB) to predict the
outcome of branch type instructions. It provides storage for the target address of branch type
instructions and predicts the next address to present to the instruction cache when the current
instruction address is that of a branch.
The BTB holds 128 entries.
2.2.2.5 Data Cache
The Intel XScale
®
microarchitecture implements a 32-Kbyte, 32-way set associative data cache
and a 2-Kbyte, 2-way set associative mini-data cache. Each cache has a line size of 32 bytes, and
supports write-through or write-back caching.
The data/mini-data cache is controlled by page attributes defined in the MMU Architecture and by
coprocessor 15.
The Intel XScale
®
microarchitecture allows applications to reconfigure a portion of the data cache
as data RAM. Software may place special tables or frequently used variables in this RAM.
2.2.2.6 Interrupt Controller
The Intel XScale ® microarchitecture provides two levels of interrupt, IRQ and FIQ. They can be
masked via coprocessor 13. Note that there is also a memory-mapped interrupt controller described
with the Intel XScale ® technology peripherals (see Section 3.12 ), which is used to mask and steer
many chip-wide interrupt sources.