2 simplex csix, Simplex csix – Intel NETWORK PROCESSOR IXP2800 User Manual

Page 278

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278

Hardware Reference Manual

Intel

®

IXP2800 Network Processor

Media and Switch Fabric Interface

The FCIFIFO supplies two signals to Microengines, which can be tested using the BR_STATE
instruction:

1. FCI_Not_Empty — indicates that there is at least one CWord in the FCIFIFO. This signal

stays asserted until all CWords have been read. (Note that when FCIFIFO is empty, this signal
will not assert until a full CFrame has been received into FCIFIFO; as that CFrame is removed

by the Microengine, this signal will stay asserted until all CWords have been removed,

including any subsequently received CFrames.)

2. FCI_Full — indicates that FCIFIFO is above the upper limit defined in

HWM_Control[FCIFIFO_Int_HWM].

The Microengine that has been assigned to handle FCIFIFO must read the CFrame, 32 bits at a

time, from the FCIFIFO by using the

msf[read]

instruction to the FCIFIFO address; the length of

the read can be anywhere from 1 to 16. The FCIFIFO handler thread must examine the Base

Header to determine how long the CFrame is and perform the necessary number of reads from the

FCIFIFO to dequeue the entire CFrame. If a read is issued to FCIFIFO when it is empty, an Idle
CFrame will be read back (0x0000FFFF). Note that when FCIFIFO is receiving a CFrame, it does

not make it visible until the entire CFrame has been received without errors.

The nearly-full signal is based on the upper limit programmed into

HWM_Control[FCIFIFO_Int_HWM]. When asserted, this means that higher priority needs to
be given to draining the FCIFIFO to prevent flow control from being asserted to the Egress

IXP2800 Network Processor (by assertion of RXCFC).

8.5.2.2

Simplex CSIX

In Simplex Mode, the Flow Control signals are connected directly to the Switch Fabric; flow

control information is sent directly from the Egress IXP2800 Network Processor to the Switch

Fabric, and directly from the Switch Fabric to the Ingress IXP2800 Network Processor.
(See

Figure 99

.)

Figure 99. CSIX Flow Control Interface — FCIFIFO and FCEFIFO in Simplex Mode

A9764-01

TDAT

RXCSRB

TXCSRB

RXCDAT, RXCPAR, RXCSOF

TXCDAT, TXCPAR, TXCSOF

RXCFC

TXCFC

RDAT

Ingress
Intel

®

IXP2800

Network Processor

Egress
Intel

®

IXP2800

Network Processor

Switch

Fabric

msf[read]

FCI_Not_Empty

FCI_Full

FCIFIFO

FCEFIFO

MSF_Rx_Control[Duplex_Mode]

From MEs

To MEs

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